Examples of CorePerfDSL descriptions
Model of the 4-stage RISC-V CPU CV32E40P.
- Modelled instructions: RV32IM
- Static branch prediction
- No memory model
Custom example to illustrate flexiblity of CorePerDSL.
- 5-stage, Harvard microarchitecture
- Modelled instructions: RV32IMC
- No, static and dynamic branch prediction
- With and without data forwarding
- Dummy memory model
This is version v1.0.
This repository does not contain any submodules.