Merge branch 'master' into integrated_bare_etiss_processor

ArchImpl/RISCV/RISCVArch.cpp

@@ -67,7 +67,8 @@ void RISCVArch::resetCPU(ETISS_CPU * cpu,etiss::uint64 * startpointer)
     else cpu->instructionPointer = 0x0;   //  reference to manual
     cpu->mode = 1;
     cpu->cpuTime_ps = 0;
-    cpu->cpuCycleTime_ps = 31250;
+    cpu->cpuCycleTime_ps = etiss::cfg(getLastAssignedCoreName())
+                                 .get<uint32_t>("arch.cpu_cycle_time_ps", 31250); // original: 31250; // 32MHz
     #if RISCV_Pipeline1 || RISCV_Pipeline2
     //Initialize resources measurements
     cpu->resources[0] = "I_RAM";

ArchImpl/RISCV64/RISCV64Arch.cpp

@@ -73,7 +73,8 @@ void RISCV64Arch::resetCPU(ETISS_CPU * cpu,etiss::uint64 * startpointer)
     else cpu->instructionPointer = 0x0;   //  reference to manual
     cpu->mode = 1;
     cpu->cpuTime_ps = 0;
-    cpu->cpuCycleTime_ps = 31250;
+    cpu->cpuCycleTime_ps = etiss::cfg(getLastAssignedCoreName())
+                                 .get<uint32_t>("arch.cpu_cycle_time_ps", 31250); // original: 31250; // 32MHz
     #if RISCV64_Pipeline1 || RISCV64_Pipeline2
     //Initialize resources measurements
     cpu->resources[0] = "I_RAM";

src/SimpleMemSystem.cpp

@@ -91,6 +91,9 @@ void SimpleMemSystem::load_segments() {
 
         ss << "simple_mem_system.memseg_length_" << std::setw(2) << std::setfill('0') << i;
         uint64_t length = etiss::cfg().get<uint64_t>(ss.str(), -1);
+        if (length == 0) {
+            etiss::log(etiss::FATALERROR, "Empty memsegs are not allowed!");
+        }
         std::stringstream().swap(ss);
 
         ss << "simple_mem_system.memseg_image_" << std::setw(2) << std::setfill('0') << i;
@@ -201,7 +204,9 @@ void SimpleMemSystem::load_elf()
     {
         etiss::uint64 start_addr = seg->get_physical_address();
         etiss::uint64 size = seg->get_memory_size();
+        if (size == 0) continue;
         size_t file_size = seg->get_file_size();
+        if (seg->get_type() != PT_LOAD) continue;
 
         int mode = 0;
         std::string modestr = "";

src/bare_etiss_processor/ETISS.ini

@@ -122,9 +122,9 @@
 
   ; Set CPU freuquency in pico seconds
   ; (or1k)   default=10000
-  ; (ARMv6M) default=31250
+  ; (RISCV)  default=31250
 
-  arch.cpu_cycle_time_ps=10000
+  arch.cpu_cycle_time_ps=31250
 
   ; Set the memory configuration of bare_etiss_processor
   ; Up to 99 segments are supported

src/bare_etiss_processor/base.ini

@@ -16,7 +16,7 @@ testing = false
 
 arch.or1k.if_stall_cycles=0
 etiss.max_block_size=100
-arch.cpu_cycle_time_ps=10000
+arch.cpu_cycle_time_ps=31250
 ETISS::CPU_quantum_ps=100000
 ETISS::write_pc_trace_from_time_us=0
 ETISS::write_pc_trace_until_time_us=3000000

src/bare_etiss_processor/get_metrics.py

@@ -1,7 +1,6 @@
 #!/usr/bin/env python
 
 import os
-import sys
 import csv
 import argparse
 import configparser
@@ -11,7 +10,7 @@
 from elftools.elf.sections import SymbolTableSection
 
 
-'''
+"""
 Script to gather metrics on ROM,RAM,Stack and Heap usage.
 
 To produce the memory trace:
@@ -21,20 +20,22 @@
 
 Then run this script:
 > ./get_metrics.py ../bin/TARGET_ELF_FILE [-i memsegs.ini]
-'''
+"""
 
 # Feel free to overwrite these defaults for your needs
 DEFAULT_RAM_START = 0x80000
 DEFAULT_RAM_SIZE = 0x80000
 DEFAULT_STACK_SIZE = 0x4000
 
+
 class MemRange:
     def __init__(self, name, min, max):
         self.name = name
         self.min = min
         self.max = max
+        assert self.min <= self.max, "Invalid MemRange"
         self.count = 0
-        self.low = 0xffffffff
+        self.low = 0xFFFFFFFF
         self.high = 0
 
     def contains(self, adr):
@@ -82,8 +83,7 @@ def parseElf(inFile):
                 m["ram_data"] += s.data_size
             elif s.name == ".rodata":
                 m["rom_rodata"] += s.data_size
-            elif (s.name == ".vectors" or
-                s.name == ".init_array"):
+            elif s.name == ".vectors" or s.name == ".init_array":
                 m["rom_misc"] += s.data_size
             elif s.name == ".data":
                 m["ram_data"] += s.data_size
@@ -109,20 +109,24 @@ def parseElf(inFile):
 
 def printSz(sz, unknown_msg=""):
     if sz is None:
-            return f"unknown [{unknown_msg}]" if unknown_msg else "unknown"
+        return f"unknown [{unknown_msg}]" if unknown_msg else "unknown"
     return humanize.naturalsize(sz) + " (" + hex(sz) + ")"
 
 
 if __name__ == "__main__":
     parser = argparse.ArgumentParser()
-    parser.add_argument('elf', metavar='ELF', type=str, nargs=1,
-                    help='The target ELF file')
-    parser.add_argument('--trace', '-t', default="dBusAccess.csv", type=str,
-            help="Path to CSV trace file of memory accesses (default: %(default)s)")
-    parser.add_argument('--ini', '-i', default="", type=str,
-            help="Path to INI file containing simple_mem_system layout (optional)")
-    parser.add_argument('--out', '-o', metavar='FILE', type=str,
-                        default="", help='''Output CSV file (default: -)''')
+    parser.add_argument("elf", metavar="ELF", type=str, nargs=1, help="The target ELF file")
+    parser.add_argument(
+        "--trace",
+        "-t",
+        default="dBusAccess.csv",
+        type=str,
+        help="Path to CSV trace file of memory accesses (default: %(default)s)",
+    )
+    parser.add_argument(
+        "--ini", "-i", default="", type=str, help="Path to INI file containing simple_mem_system layout (optional)"
+    )
+    parser.add_argument("--out", "-o", metavar="FILE", type=str, default="", help="""Output CSV file (default: -)""")
     args = parser.parse_args()
 
     elfFile = args.elf[0]
@@ -174,7 +178,7 @@ def printSz(sz, unknown_msg=""):
     if os.path.exists(traceFile):
         trace_available = True
         with open(traceFile) as f:
-            reader = csv.reader(f, skipinitialspace=True, delimiter=';')
+            reader = csv.reader(f, skipinitialspace=True, delimiter=";")
             for r in reader:
                 adr = int(r[2], 16)
                 for mem in mems:
@@ -196,23 +200,27 @@ def printSz(sz, unknown_msg=""):
         "ram_data": staticSizes["ram_data"],
         "ram_zdata": staticSizes["ram_zdata"],
         "ram_stack": s.usage() if trace_available else None,
-        "ram_heap": h.usage() if trace_available else None
+        "ram_heap": h.usage() if trace_available else None,
     }
 
     print("=== Results ===")
     print("ROM usage:        " + printSz(results["rom"]))
     print("  read-only data: " + printSz(results["rom_rodata"]))
     print("  code:           " + printSz(results["rom_code"]))
     print("  other required: " + printSz(results["rom_misc"]))
-    print("RAM usage:        " + printSz(results["ram"]) + ("" if trace_available else " [stack and heap usage not included]"))
+    print(
+        "RAM usage:        "
+        + printSz(results["ram"])
+        + ("" if trace_available else " [stack and heap usage not included]")
+    )
     print("  data:           " + printSz(results["ram_data"]))
     print("  zero-init data: " + printSz(results["ram_zdata"]))
     print("  stack:          " + printSz(results["ram_stack"], unknown_msg="missing trace file"))
     print("  heap:           " + printSz(results["ram_heap"], unknown_msg="missing trace file"))
 
     # Write metrics to file
     if csvFile:
-        with open(csvFile, 'w') as f:
+        with open(csvFile, "w") as f:
             writer = csv.DictWriter(f, fieldnames=results.keys())
             writer.writeheader()
             writer.writerow(results)