uPD77C25: implement SGN as virtual register

twvd · Jan 10, 2024 · 02d37e7 · 02d37e7
1 parent b4ba65d
commit 02d37e7
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Showing 2 changed files with 24 additions and 6 deletions.
diff --git a/src/snes/cpu_upd77c25/cpu.rs b/src/snes/cpu_upd77c25/cpu.rs
@@ -381,7 +381,7 @@ mod tests {
     fn ld_nop() {
         let c = cpu_run(0b11_1010101010101010_00_0000);
         assert!(Register::iter()
-            .filter(|&r| r != Register::PC)
+            .filter(|&r| r != Register::PC && r != Register::SGN)
             .all(|r| c.regs.read(r) == 0));
     }
 
@@ -390,7 +390,7 @@ mod tests {
         let test = |op, reg| {
             let c = cpu_run(op);
             assert!(Register::iter()
-                .filter(|&r| r != Register::PC && r != reg)
+                .filter(|&r| r != Register::PC && r != Register::SGN && r != reg)
                 .all(|r| c.regs.read(r) == 0));
             assert_ne!(c.regs.read(reg), 0);
         };

diff --git a/src/snes/cpu_upd77c25/regs.rs b/src/snes/cpu_upd77c25/regs.rs
@@ -117,7 +117,6 @@ impl Register {
 pub struct RegisterFile {
     pub acca: u16,
     pub accb: u16,
-    pub sgn: u16,
     pub k: u16,
     pub l: u16,
     pub m: u16,
@@ -139,7 +138,6 @@ impl RegisterFile {
         Self {
             acca: 0,
             accb: 0,
-            sgn: 0,
             k: 0,
             l: 0,
             m: 0,
@@ -166,7 +164,6 @@ impl RegisterFile {
             // Pure 16-bit registers
             Register::ACCA => self.acca = val,
             Register::ACCB => self.accb = val,
-            Register::SGN => self.sgn = val,
             Register::K => self.k = val,
             Register::L => self.l = val,
             Register::M => self.m = val,
@@ -185,6 +182,9 @@ impl RegisterFile {
             Register::RP => self.rp = val & 0x3FF,
             // 11-bit
             Register::PC => self.pc = val & 0x7FF,
+
+            // Virtual register
+            Register::SGN => unreachable!(),
         }
     }
 
@@ -194,7 +194,6 @@ impl RegisterFile {
             // Pure 16-bit registers
             Register::ACCA => self.acca,
             Register::ACCB => self.accb,
-            Register::SGN => self.sgn,
             Register::K => self.k,
             Register::L => self.l,
             Register::M => self.m,
@@ -209,6 +208,10 @@ impl RegisterFile {
 
             // 4-bit
             Register::SP => self.sp.into(),
+
+            // Virtual register
+            Register::SGN if self.test_flag(Flags::A, Flag::S1) => 0x7FFF,
+            Register::SGN => 0x8000,
         }
     }
 
@@ -575,4 +578,19 @@ mod tests {
         r.write_sr(&[(SR::O1, true)]);
         assert!(r.test_sr(SR::O0));
     }
+
+    #[test]
+    fn read_sgn() {
+        let mut r = RegisterFile::new();
+        assert_eq!(r.read(Register::SGN), 0x8000);
+        r.write_flags(Flags::A, &[(Flag::S1, true)]);
+        assert_eq!(r.read(Register::SGN), 0x7FFF);
+    }
+
+    #[test]
+    #[should_panic]
+    fn write_sgn() {
+        let mut r = RegisterFile::new();
+        r.write(Register::SGN, 0);
+    }
 }