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Fix DMA mode 1 length
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twvd committed Oct 29, 2023
1 parent 5c9af5e commit 72fb230
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Showing 2 changed files with 22 additions and 35 deletions.
51 changes: 19 additions & 32 deletions src/snes/bus/mainbus.rs
Original file line number Diff line number Diff line change
Expand Up @@ -107,11 +107,11 @@ impl DMAChannel {
}
}

pub fn len(&self) -> usize {
pub fn len(&self) -> Address {
if self.das == 0 {
0x10000
} else {
self.das as usize
Address::from(self.das + (self.das % 4))
}
}

Expand Down Expand Up @@ -152,46 +152,33 @@ where
dbg_hex!(&self.dma[ch]);
}

match self.dma[ch].mode() {
0 => {
for i in 0..(self.dma[ch].len() as Address) {
let b_addr = self.dma[ch].b_addr();
match self.dma[ch].direction() {
DMADirection::CPUToIO => {
let a_addr = match self.dma[ch].step() {
DMAStep::Increment => self.dma[ch].a_addr() + i,
DMAStep::Fixed => self.dma[ch].a_addr(),
_ => todo!(),
};

let v = self.read(a_addr);
self.write(b_addr, v);
}
_ => todo!(),
for i in 0..self.dma[ch].len() {
let b_addr = self.dma[ch].b_addr();
let a_addr = match self.dma[ch].step() {
DMAStep::Increment => self.dma[ch].a_addr() + i,
DMAStep::Fixed => self.dma[ch].a_addr(),
_ => todo!(),
};
match self.dma[ch].mode() {
0 => match self.dma[ch].direction() {
DMADirection::CPUToIO => {
let v = self.read(a_addr);
self.write(b_addr, v);
}
}
}
1 => {
for i in 0..(self.dma[ch].len() as Address) {
let b_addr = self.dma[ch].b_addr();
_ => todo!(),
},
1 => {
let b_addr = b_addr + (i & 1);
match self.dma[ch].direction() {
DMADirection::CPUToIO => {
let a_addr = match self.dma[ch].step() {
DMAStep::Increment => self.dma[ch].a_addr() + (i * 2),
DMAStep::Fixed => self.dma[ch].a_addr(),
_ => todo!(),
};

let v = self.read(a_addr);
self.write(b_addr, v);
let v2 = self.read(a_addr + 1);
self.write(b_addr + 1, v2);
}
_ => todo!(),
}
}
_ => todo!(),
}
_ => todo!(),
}
}
}
Expand Down
6 changes: 3 additions & 3 deletions src/snes/ppu/mod.rs
Original file line number Diff line number Diff line change
Expand Up @@ -20,12 +20,12 @@ type VramWord = u16;
const VRAM_WORDS: usize = 32 * 1024;
const VRAM_WORDSIZE: usize = 2;
// 32K-words addressable (64KB)
const VRAM_ADDRMASK: usize = 0x7FFF;
const VRAM_ADDRMASK: usize = VRAM_WORDS - 1;

type CgramWord = u16;
const CGRAM_WORDS: usize = 256;
const CGRAM_WORDSIZE: usize = 2;
const CGRAM_ADDRMASK: usize = 0xFF;
const CGRAM_ADDRMASK: usize = CGRAM_WORDS - 1;

// VMAIN bits
const VMAIN_HIGH: u8 = 1 << 7;
Expand Down Expand Up @@ -202,7 +202,7 @@ where
0 => {
if !self.is_layer_16x16(bg) {
let tm_x = x / 8;
let tm_y = y.rem_euclid(32 * 8) / 8;
let tm_y = y % (32 * 8) / 8;
self.get_tilemap_entry(bg, tm_x + (tm_y * 32))
} else {
todo!()
Expand Down

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