GSU: fix up and test SBK

twvd · Feb 28, 2024 · 927363d · 927363d
1 parent 8737441
commit 927363d
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Showing 3 changed files with 64 additions and 13 deletions.
diff --git a/src/cpu_gsu/cpu.rs b/src/cpu_gsu/cpu.rs
@@ -36,7 +36,7 @@ pub struct CpuGsu {
     pub dreg: usize,
     branch_pc: Option<u16>,
     irq_pending: bool,
-    last_ramaddr: usize,
+    last_ramaddr: u16,
 
     pub cache_valid: [bool; CACHE_LINES],
 }
@@ -364,7 +364,7 @@ impl CpuGsu {
                     self.ram[addr_l] = v as u8;
                     self.ram[addr_h] = (v >> 8) as u8;
                 }
-                self.last_ramaddr = addr as usize;
+                self.last_ramaddr = addr;
                 self.cycles(1)?;
             }
             (0x30..=0x3B, true, false) => {
@@ -374,7 +374,7 @@ impl CpuGsu {
                 let v = self.regs.read_r(sreg);
                 // Ignores high byte
                 self.ram[addr] = v as u8;
-                self.last_ramaddr = addr;
+                self.last_ramaddr = addr as u16;
                 self.cycles(1)?;
             }
             (0x3C, false, false) => {
@@ -419,7 +419,7 @@ impl CpuGsu {
                     self.ram[addr_l] as u16 | ((self.ram[addr_h] as u16) << 8)
                 };
 
-                self.last_ramaddr = addr_l;
+                self.last_ramaddr = addr;
                 self.regs.write_r(dreg, v);
                 self.cycles(7)?;
             }
@@ -429,7 +429,7 @@ impl CpuGsu {
                     | usize::from(self.regs.read_r((instr & 0x0F) as usize));
                 // Zero-expanded
                 let v = self.ram[addr_l] as u16;
-                self.last_ramaddr = addr_l;
+                self.last_ramaddr = addr_l as u16;
                 self.regs.write_r(dreg, v);
                 self.cycles(6)?;
             }
@@ -660,17 +660,17 @@ impl CpuGsu {
             }
             (0x90, false, false) => {
                 // SBK
-                let addr = self.last_ramaddr;
+                let addr = usize::from(self.regs.read(Register::RAMBR)) << 16
+                    | usize::from(self.last_ramaddr);
                 let v = self.regs.read_r(sreg);
 
                 if addr & 1 != 0 {
-                    self.ram[(addr & !1) + 1] = v as u8;
+                    self.ram[addr | 1] = v as u8;
                     self.ram[addr & !1] = (v >> 8) as u8;
                 } else {
                     self.ram[addr & !1] = v as u8;
-                    self.ram[(addr & !1) + 1] = (v >> 8) as u8;
+                    self.ram[addr | 1] = (v >> 8) as u8;
                 }
-                self.last_ramaddr = addr;
                 self.cycles(1)?;
             }
             (0x91..=0x94, false, false) => {
@@ -801,7 +801,7 @@ impl CpuGsu {
                     | usize::from(yy.wrapping_add(1));
 
                 let val = ((self.ram[addr_h] as u16) << 8) | (self.ram[addr_l] as u16);
-                self.last_ramaddr = addr_l;
+                self.last_ramaddr = yy;
                 self.regs.write_r(reg, val);
                 self.cycles(7)?;
             }
@@ -816,7 +816,7 @@ impl CpuGsu {
                 let val = self.regs.read_r(reg);
                 self.ram[addr_l] = val as u8;
                 self.ram[addr_h] = (val >> 8) as u8;
-                self.last_ramaddr = addr_l;
+                self.last_ramaddr = yy;
                 self.cycles(1)?;
             }
             (0xB0..=0xBF, _, _) => {
@@ -985,7 +985,7 @@ impl CpuGsu {
                     self.ram[addr_l] = val as u8;
                     self.ram[addr_h] = (val >> 8) as u8;
                 }
-                self.last_ramaddr = yy as usize;
+                self.last_ramaddr = yy;
                 self.cycles(4)?;
             }
             (0xF0..=0xFF, true, false) => {
@@ -1004,7 +1004,7 @@ impl CpuGsu {
                 } else {
                     ((self.ram[addr_h] as u16) << 8) | (self.ram[addr_l] as u16)
                 };
-                self.last_ramaddr = yy as usize;
+                self.last_ramaddr = yy;
                 self.regs.write_r(reg, val);
                 self.cycles(4)?;
             }

diff --git a/src/cpu_gsu/test.rs b/src/cpu_gsu/test.rs
@@ -17,6 +17,7 @@ const LM: u8 = 0xF0;
 const LMS: u8 = 0xA0;
 const SM: u8 = 0xF0;
 const SMS: u8 = 0xA0;
+const SBK: u8 = 0x90;
 
 fn cpu(code: &[u8]) -> CpuGsu {
     let c = CpuGsu::new(code);
@@ -275,3 +276,46 @@ fn op_sms() {
     assert_eq!(c.ram[0x10], 0xBB);
     assert_eq!(c.ram[0x11], 0xAA);
 }
+
+#[test]
+fn op_sbk() {
+    let c = cpu_ram_steps(
+        &[
+            IWT | 4,
+            0x22,
+            0x11,
+            IWT | 5,
+            0xDD,
+            0xCC,
+            TO | 3,
+            LDW | 4,
+            FROM | 5,
+            SBK,
+        ],
+        &[(0x1122, 0xBB), (0x1123, 0xAA)],
+        6,
+    );
+    assert_eq!(c.regs.read(Register::R3), 0xAABB);
+    assert_eq!(c.ram[0x1122], 0xDD);
+    assert_eq!(c.ram[0x1123], 0xCC);
+
+    let c = cpu_ram_steps(
+        &[
+            IWT | 4,
+            0x23,
+            0x11,
+            IWT | 5,
+            0xDD,
+            0xCC,
+            TO | 3,
+            LDW | 4,
+            FROM | 5,
+            SBK,
+        ],
+        &[(0x1122, 0xBB), (0x1123, 0xAA)],
+        6,
+    );
+    assert_eq!(c.regs.read(Register::R3), 0xBBAA);
+    assert_eq!(c.ram[0x1122], 0xCC);
+    assert_eq!(c.ram[0x1123], 0xDD);
+}
diff --git a/src/snes/coprocessor/superfx.rs b/src/snes/coprocessor/superfx.rs
@@ -32,6 +32,13 @@ impl Tickable for SuperFX {
     fn tick(&mut self, ticks: Ticks) -> Result<()> {
         let mut cpu = self.cpu.borrow_mut();
 
+        cpu.tick(ticks)?;
+        cpu.tick(ticks)?;
+        cpu.tick(ticks)?;
+        cpu.tick(ticks)?;
+        cpu.tick(ticks)?;
+        cpu.tick(ticks)?;
+        cpu.tick(ticks)?;
         cpu.tick(ticks)?;
         Ok(())
     }