65816: implement load ops with immediate addressing modes

twvd · Oct 16, 2023 · cb4882f · cb4882f
1 parent 53479f6
commit cb4882f
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Showing 2 changed files with 33 additions and 3 deletions.
diff --git a/src/snes/cpu_65816/cpu.rs b/src/snes/cpu_65816/cpu.rs
@@ -191,6 +191,16 @@ where
             InstructionType::STA => self.op_stx_reg(&instr, Register::C, Flag::M),
             InstructionType::STX => self.op_stx_reg(&instr, Register::X, Flag::X),
             InstructionType::STY => self.op_stx_reg(&instr, Register::Y, Flag::X),
+            InstructionType::LDA if instr.def.mode == AddressingMode::ImmediateM => {
+                self.op_load_imm(&instr, Register::C, Flag::M)
+            }
+            InstructionType::LDX if instr.def.mode == AddressingMode::ImmediateX => {
+                self.op_load_imm(&instr, Register::X, Flag::X)
+            }
+            InstructionType::LDY if instr.def.mode == AddressingMode::ImmediateX => {
+                self.op_load_imm(&instr, Register::Y, Flag::X)
+            }
+
             InstructionType::LDA => self.op_load(&instr, Register::C, Flag::M),
             InstructionType::LDX => self.op_load(&instr, Register::X, Flag::X),
             InstructionType::LDY => self.op_load(&instr, Register::Y, Flag::X),
@@ -531,4 +541,24 @@ where
 
         Ok(())
     }
+
+    /// Load operations (immediate addressing mode)
+    fn op_load_imm(&mut self, instr: &Instruction, destreg: Register, flag: Flag) -> Result<()> {
+        if self.regs.test_flag(flag) {
+            // 8-bit mode
+            let val = instr.imm::<u8>()?;
+            let regval = self.regs.read(destreg);
+            self.regs.write(destreg, regval & 0xFF00 | val as u16);
+            self.regs
+                .write_flags(&[(Flag::N, val & 0x80 != 0), (Flag::Z, val == 0)]);
+        } else {
+            // 16-bit mode
+            let val = instr.imm::<u16>()?;
+            self.regs.write(destreg, val);
+            self.regs
+                .write_flags(&[(Flag::N, val & 0x8000 != 0), (Flag::Z, val == 0)]);
+        }
+
+        Ok(())
+    }
 }
diff --git a/src/test/processortests_65816.rs b/src/test/processortests_65816.rs
@@ -299,16 +299,16 @@ cpu_test!(instr_9c, 0x9c);
 cpu_test!(instr_9d, 0x9d);
 cpu_test!(instr_9e, 0x9e);
 cpu_test!(instr_9f, 0x9f);
-//cpu_test!(instr_a0, 0xa0);
+cpu_test!(instr_a0, 0xa0);
 cpu_test!(instr_a1, 0xa1);
-//cpu_test!(instr_a2, 0xa2);
+cpu_test!(instr_a2, 0xa2);
 cpu_test!(instr_a3, 0xa3);
 cpu_test!(instr_a4, 0xa4);
 cpu_test!(instr_a5, 0xa5);
 cpu_test!(instr_a6, 0xa6);
 cpu_test!(instr_a7, 0xa7);
 cpu_test!(instr_a8, 0xa8);
-//cpu_test!(instr_a9, 0xa9);
+cpu_test!(instr_a9, 0xa9);
 cpu_test!(instr_aa, 0xaa);
 //cpu_test!(instr_ab, 0xab);
 cpu_test!(instr_ac, 0xac);