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Fix rebooting Macintosh Plus
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twvd committed Nov 29, 2024
1 parent dad82c8 commit b8a616f
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Showing 4 changed files with 17 additions and 0 deletions.
4 changes: 4 additions & 0 deletions core/src/bus/mod.rs
Original file line number Diff line number Diff line change
Expand Up @@ -2,6 +2,7 @@ pub mod testbus;

use crate::tickable::Tickable;

use anyhow::Result;
use num_traits::{PrimInt, WrappingAdd};

/// Main CPU address data type (actually 24-bit)
Expand Down Expand Up @@ -34,6 +35,9 @@ pub trait Bus<TA: PrimInt + WrappingAdd, TD: PrimInt>: Tickable {
fn read(&mut self, addr: TA) -> BusResult<TD>;
fn write(&mut self, addr: TA, val: TD) -> BusResult<TD>;
fn get_mask(&self) -> TA;

/// RESET line triggered by 68k RESET instruction
fn reset(&mut self) -> Result<()>;
}

/// Inspectable provides an interface to debugging/memory views.
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4 changes: 4 additions & 0 deletions core/src/bus/testbus.rs
Original file line number Diff line number Diff line change
Expand Up @@ -102,6 +102,10 @@ where
self.mem.insert(addr, val);
BusResult::Ok(val)
}

fn reset(&mut self) -> Result<()> {
Ok(())
}
}

impl<TA, TD> Tickable for Testbus<TA, TD>
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2 changes: 2 additions & 0 deletions core/src/cpu_m68k/cpu.rs
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Expand Up @@ -2046,6 +2046,8 @@ where
return self.raise_exception(ExceptionGroup::Group2, VECTOR_PRIVILEGE_VIOLATION, None);
}

debug!("RESET instruction");
self.bus.reset()?;
self.advance_cycles(128)?;
Ok(())
}
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7 changes: 7 additions & 0 deletions core/src/mac/bus.rs
Original file line number Diff line number Diff line change
Expand Up @@ -443,6 +443,13 @@ where
}
BusResult::Ok(val)
}

fn reset(&mut self) -> Result<()> {
self.via = Via::new(self.model);
self.scc = Scc::new();
self.overlay = true;
Ok(())
}
}

impl<TRenderer> Tickable for MacBus<TRenderer>
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