Hardware Simulator and Assembler

Website

Description:

A Hardware Simulator and an Assembler with its own assembly language, with several Instruction Set, Memory, I/O Architectures supported.

Architectures:

• Instruction Set Architecture (Register Architecture)

  1. Stack (Zero-Address)

  2. Accumulator (One-Address)

  3. Register (Two-Address)

• Instruction Set Complexity

  1. Reduced Instruction Set Computer (RISC)

  2. Complex Instruction Set Computer (CISC)

• General Memory Architecture

  1. Von Neumann (Princeton) architecture

  2. Harvard architecture

  3. Modified Harvard architecture

• Input/Output

  1. Memory-Mapped I/O

  2. Separate Space MMIO

  3. Special commands

• SIMD

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Usage for Contributing

# Testing
git clone https://github.com/dariaomelkina/poc_project
# Assembler:
python3 modules/assembler.py -f modules/program_examples/assembly_test.asm --isa RISC3
# Simulator:
python3 modules/simulator.py --file modules/program_examples/assembly_test6.bin --isa RISC3 --architecture neumann --output special
# Fork, Edit and open Pull Requests or Issues

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General project layout

You should not, under any circumstances try to understand what's going on there

• ./docs contains the specs and docs we started this project with, and a 'help' document representing the current state of things with, supposedly, human-readable documentation
• ./modules contains the general 'backend' modules of the project, an assembler and a hardware simulator
• ./website contains the general 'frontend' modules of the project, the things running the simulator web page and help pages

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Prerequisites:

Admittedly, there are a lot of those, but we plan (do we really?) to rewrite the front-end without using Dash.

pip install -r requirements.txt

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Testing:

python3 modules/test_assembler.py
python3 modules/test_processor.py
# After every run, there is a detailed log saved in ./log.txt
less log.txt

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Credits:

• Oleg Farenyuk
• Daria Omelkina
• Andriy Sultanov

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License:

GNU General Public License v3.0