Merge pull request #4 from veryl-lang/move_test

Move tests to embed block in Veryl code

Veryl.toml

@@ -11,3 +11,9 @@ target = {type = "directory", path = "target/src"}
 
 [doc]
 path = "target/doc"
+
+[test.vcs]
+compile_args = ["-full64"]
+
+[test.verilator]
+compile_args = ["-Wno-MULTIDRIVEN", "-Wno-WIDTHTRUNC", "-Wno-WIDTHEXPAND"]

src/binary_enc_dec/binary_decoder.veryl

@@ -63,3 +63,28 @@ module _bin_decoder #(
         assign o_unary = {r_unary, r_unary} & {mask_top, mask_bot};
     }
 }
+
+#[test(test_binary_decoder)]
+embed (inline) sv{{{
+module test_binary_decoder;
+
+  parameter BIN_WIDTH = 8;
+  parameter UNARY_WIDTH = 1 << BIN_WIDTH;
+
+  logic i_en;
+  logic [BIN_WIDTH-1:0] i_bin;
+  logic [UNARY_WIDTH-1:0] o_unary;
+
+  std_binary_decoder #(BIN_WIDTH) dut (.*);
+
+  initial begin
+    i_en = 1'b1;
+
+    for (longint i = 0; i < UNARY_WIDTH; ++i) begin
+      i_bin = i;
+      #1 assert($onehot(o_unary));
+      assert(o_unary[i_bin] == 1'b1) else $error("error detected");
+    end
+  end
+endmodule
+}}}

src/binary_enc_dec/binary_encoder.veryl

@@ -86,3 +86,27 @@ module _binary_encoder #(
     }
 
 }
+
+#[test(test_binary_encoder)]
+embed (inline) sv{{{
+module test_binary_encoder;
+
+  parameter BIN_WIDTH = 8;
+  parameter UNARY_WIDTH = 1 << BIN_WIDTH;
+
+  logic i_en;
+  logic [BIN_WIDTH-1:0] o_bin;
+  logic [UNARY_WIDTH-1:0] i_unary;
+
+  std_binary_encoder #(UNARY_WIDTH) dut (.*);
+
+  initial begin
+    i_en = 1'b1;
+
+    for (longint i = 0; i < UNARY_WIDTH; ++i) begin
+      #1 i_unary = 1 << i;
+      #1 assert(i_unary[o_bin] == 1'b1) else $error("error detected");
+    end
+  end
+endmodule
+}}}

src/delay/delay.veryl

@@ -22,7 +22,7 @@ pub module delay #(
         assign o_d = delay[DELAY - 1];
         always_ff (i_clk, i_rst) {
             if_reset {
-                delay = '0;
+                delay = '{0};
             } else {
                 delay[0] = i_d;
                 for i: u32 in 1..DELAY {

src/gray/bin2gray.veryl

@@ -12,3 +12,35 @@ pub module bin2gray #(
 ) {
     assign o_gray = i_bin ^ (i_bin >> 1);
 }
+
+#[test(test_gray)]
+embed (inline) sv{{{
+module test_gray;
+  localparam WIDTH = 16;
+  logic [WIDTH-1:0] i_bin;
+  logic [WIDTH-1:0] o_gray;
+  logic [WIDTH-1:0] o_bin;
+  logic [WIDTH-1:0] g_bin;
+
+  always_comb begin
+    g_bin = '0;
+    for (int i = 0; i < WIDTH; ++i) begin
+      g_bin ^= o_gray >> i;
+    end
+  end
+
+  std_bin2gray #(WIDTH) dut2(.i_bin, .o_gray);
+  std_gray2bin #(WIDTH) dut1(.i_gray(o_gray), .o_bin);
+
+  initial begin
+    for (longint i = 0; i < (1 << WIDTH); ++i) begin
+      i_bin = i;
+      #1;
+      assert(o_bin == g_bin) else $error("error detected");
+      assert(i_bin == o_bin) else $error("error detected");
+      #1;
+    end
+  end
+
+endmodule
+}}}

src/lfsr/lfsr_galois.veryl

@@ -110,3 +110,89 @@ pub module lfsr_galois #(
         }
     }
 }
+
+#[test(test_lfsr_galois)]
+embed (inline) sv{{{
+module test_lfsr_galois;
+    parameter MAXSIZE = 24;
+    parameter MINSIZE = 2;
+
+    logic [MAXSIZE-1:MINSIZE] done;
+    logic [MAXSIZE-1:MINSIZE] working;
+    logic i_clk;
+
+    for (genvar i = MINSIZE; i < MAXSIZE; ++i) begin
+        initial $info("Spawning LFSR of Size %d", i);
+        lfsr_galois_bench #(.SIZE(i)) u_lfsr(.i_clk, .done(done[i]), .working(working[i]));
+    end
+    default clocking
+      @(posedge i_clk);
+    endclocking
+
+    initial forever begin
+        ##4
+        if (&done) begin
+            if (|working) begin
+                $info("Finishing Simulations with \033[32m100%% Success\033[0m");
+            end else begin
+                $error("Finishing Simulations with \033[31mErrors\033[0m");
+            end
+            $finish;
+        end
+    end
+
+  initial begin
+    i_clk = 1'b0;
+    forever #5 i_clk = ~i_clk;
+  end
+endmodule
+
+module lfsr_galois_bench #(parameter SIZE=64) (input i_clk, output logic done, output logic working);
+  logic [SIZE:0] limit;
+
+
+  logic i_en, i_set;
+  logic [SIZE-1:0] i_setval;
+  logic [SIZE-1:0] o_val;
+
+  std_lfsr_galois #(.SIZE(SIZE)) dut (.*);
+
+
+  default clocking
+    @(posedge i_clk);
+  endclocking
+
+
+  initial begin
+    int outvecs [logic[SIZE-1:0]];
+    working = 1'b1;
+    $info("Begining LFSR of Size %d", SIZE);
+    done = 1'b0;
+    i_en = 1'b1;
+    i_set = 1'b1;
+    i_setval = 16'h0001;
+
+    ##2;
+
+    i_set = 1'b0;
+    limit = '1;
+    limit[0] = 1'b0; 
+    limit[SIZE] = 1'b0;
+
+    for (int i = 0; i < limit; i += 1) begin
+      ##1;
+      assert(0 == outvecs.exists(o_val));
+      working &= !outvecs.exists(o_val);
+      outvecs[o_val] = 1'b1;
+    end
+
+    done = 1'b1;
+
+    if (working) 
+        $info("Succesfully Ending LFSR of Size %0d", SIZE);
+    else
+        $error("Failure Detecing in LFSR of size %0d", SIZE);
+  end
+
+endmodule
+}}}