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Enable naming lint #8

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Aug 21, 2024
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21 changes: 21 additions & 0 deletions Veryl.toml
Original file line number Diff line number Diff line change
Expand Up @@ -10,6 +10,27 @@ repository = "https://github.com/veryl-lang/std"
target = {type = "directory", path = "target/src"}
exclude_std = true

[lint.naming]
case_enum = "snake"
case_function = "snake"
case_instance = "snake"
case_interface = "snake"
case_modport = "snake"
case_module = "snake"
case_package = "snake"
case_parameter = "screaming_snake"
case_port_inout = "snake"
case_port_input = "snake"
case_port_modport = "snake"
case_port_output = "snake"
case_reg = "snake"
case_struct = "snake"
case_union = "snake"
case_var = "snake"
case_wire = "snake"
prefix_port_input = "i"
prefix_port_output = "o"

[doc]
path = "target/doc"

Expand Down
22 changes: 11 additions & 11 deletions src/lfsr/lfsr_galois.veryl
Original file line number Diff line number Diff line change
@@ -1,10 +1,10 @@
pub module lfsr_galois #(
/// Size of the LFSR in bits
param SIZE : u32 = 64 ,
local tapvec: type = logic<SIZE>,
param SIZE : u32 = 64 ,
local TAPVEC_T: type = logic<SIZE>,
/// Bit-vector representing the taps of the LFSR.
/// Default values provided for `SIZE` in range [2, 64]
param TAPVEC: tapvec = case SIZE {
param TAPVEC: TAPVEC_T = case SIZE {
2 : 2'h3,
3 : 3'h5,
4 : 4'h9,
Expand Down Expand Up @@ -88,18 +88,18 @@ pub module lfsr_galois #(

assign val_next[SIZE - 1] = o_val[0];
for i in 0..(SIZE - 1) :g_taps {
local k: u32 = SIZE - 2 - i;
if TAPVEC[k] :g_tap {
assign val_next[k] = if i_set {
i_setval[k]
local K: u32 = SIZE - 2 - i;
if TAPVEC[K] :g_tap {
assign val_next[K] = if i_set {
i_setval[K]
} else {
o_val[k + 1] ^ o_val[0]
o_val[K + 1] ^ o_val[0]
};
} else :g_notap {
assign val_next[k] = if i_set {
i_setval[k]
assign val_next[K] = if i_set {
i_setval[K]
} else {
o_val[k + 1]
o_val[K + 1]
};
}
}
Expand Down