Add reference to verilog-instance plugin in the README #149
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Hi Vitor,
I just added this vim plugin:
https://github.com/antoinemadec/vim-verilog-instance
This creates SystemVerilog port instantiation from port declaration.
It is saving me a lot of time when I code in Verilog.
I have been using it for years now and I just found the courage to add features, re write it and release it to the world.
I was wondering if you could add it to the "Other vim plugins for Verilog/SystemVerilog" section of verilog_systemverilog's README ?
Also, feel free to report bugs or give me advice to make the plug-in clearer and cleaner.
Thanks in advance,
Antoine