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cleanups, minor (useless ?) fix to GTS3 alphaseg
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@vbousquet
vbousquet committed Sep 26, 2024
1 parent 1a2f0a1 commit 0768b32
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Showing 5 changed files with 67 additions and 78 deletions.
3 changes: 1 addition & 2 deletions docs/dmd.md
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Expand Up @@ -12,8 +12,7 @@ accurately (mainly for backward compatibility, since this was the only thing ava

All DMD control board use Pulse Width Modulation (PWM) to create shades: they quickly toggle the dots on and
off, and the observer eye perceive a shade between fully off and fully on. The limit between perceiving flicker vs perceiving
a stable shade is called the flicker/fusion limit and has lots of scientific documentation as this is a key point when
designing a display. It depends mainly on 2 factors:
a stable shade is called the [flicker/fusion threshold](https://en.wikipedia.org/wiki/Flicker_fusion_threshold). It depends mainly on 2 factors:
- the speed at which the dots switch on/off (do they ramp up/down quickly or do they fade more slowly),
- the device luminance level, which impacts how the human eye perceive light (Ferry/Porter law).

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12 changes: 6 additions & 6 deletions src/p-roc/p-roc.cpp
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Expand Up @@ -95,12 +95,12 @@ PRMachineType getRomMachineType() {
switch (core_gameData->gen) {
case GEN_WPCALPHA_1:
case GEN_WPCALPHA_2:
case GEN_DE:
case GEN_S4:
case GEN_S11A:
case GEN_S11:
case GEN_S11B2:
case GEN_S11C:
case GEN_DE:
case GEN_S4:
case GEN_S11A:
case GEN_S11:
case GEN_S11B2:
case GEN_S11C:
if (pmoptions.alpha_on_dmd) {
fprintf(stderr, "ROM machine type: kPRMachineWPCAlphanumeric,\nbut using kPRMachineWPC due to alpha_on_dmd option\n");
return kPRMachineWPC;
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59 changes: 22 additions & 37 deletions src/wpc/gts3.c
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Expand Up @@ -158,11 +158,9 @@ static WRITE_HANDLER( xvia_0_b_w ) {
// - LCLR H->L / LCLR L->H
// We do not simulate the LCLR signals since the pulse is too short (50us) for the output resolution
//printf("t=%8.5f Col=%3x STRB=%d DATA=%d LCLR=%d\n", timer_get_time(), GTS3locals.lampColumn, data & LSTRB, data & LDATA, data & LCLR);
if (data & ~GTS3locals.u4pb & LSTRB) // Positive edge on LSTRB: shift 12bit register and set bit0 to LDATA
{
if (~GTS3locals.u4pb & data & LSTRB) { // Positive edge on LSTRB: shift 12bit register and set bit0 to LDATA
GTS3locals.lampColumn = ((GTS3locals.lampColumn << 1) & 0x0ffe) | (data & LDATA);
if (GTS3locals.lampColumn == 0x001) // Simple strobe emulation: accumulate lamp matrix until strobe restarts from first column
{
if (GTS3locals.lampColumn == 0x001) { // Simple strobe emulation: accumulate lamp matrix until strobe restarts from first column
memcpy(coreGlobals.lampMatrix, coreGlobals.tmpLampMatrix, sizeof(coreGlobals.tmpLampMatrix));
memset(coreGlobals.tmpLampMatrix, 0, sizeof(coreGlobals.tmpLampMatrix));
}
Expand All @@ -172,11 +170,8 @@ static WRITE_HANDLER( xvia_0_b_w ) {
core_write_pwm_output_lamp_matrix(CORE_MODOUT_LAMP0 + 64, (GTS3locals.lampColumn >> 8) & 0x0F, lampRow, 4);


if (GTS3locals.alphagen)
{ // Alpha generation
//printf("%8.5f Alpha Strobe %02x %05x\n", timer_get_time(), data, GTS3locals.alphaNumColShiftRegister);
if (data & ~GTS3locals.u4pb & DSTRB) // Positive edge on DSTRB: shift 20bit register and set bit0 to DDATA
{
if (GTS3locals.alphagen) { // Alpha generation
if (~GTS3locals.u4pb & data & DSTRB) { // Positive edge on DSTRB: shift 20bit register and set bit0 to DDATA
core_write_pwm_output_8b(CORE_MODOUT_SEG0 + (GTS3locals.alphaNumCol + 20) * 16, 0);
core_write_pwm_output_8b(CORE_MODOUT_SEG0 + (GTS3locals.alphaNumCol + 20) * 16 + 8, 0);
core_write_pwm_output_8b(CORE_MODOUT_SEG0 + (GTS3locals.alphaNumCol ) * 16 , 0);
Expand All @@ -186,29 +181,21 @@ static WRITE_HANDLER( xvia_0_b_w ) {
// This should never happens but you can drive the hardware to it (multiple resets,...), this will lead to incorrect rendering
// assert((GTS3locals.alphaNumColShiftRegister == 0) || (GTS3locals.alphaNumColShiftRegister == (1 << GTS3locals.alphaNumCol)));
}
if (data & ~GTS3locals.u4pb & DBLNK) // DBlank start (positive edge)
{
if (~GTS3locals.u4pb & data & DBLNK) { // DBlank start (positive edge)
for (int i = 0; i < 20 * 2 * 2; i++)
core_write_pwm_output_8b(CORE_MODOUT_SEG0 + i * 8, 0);
}
else if (GTS3locals.alphaNumCol < 20) {
if (~data & GTS3locals.u4pb & DBLNK) // DBlank end (negative edge)
{
// Basic non dimmed segments emulation: just use the column and value defined during DBLNK
coreGlobals.segments[GTS3locals.alphaNumCol + 20].w = GTS3locals.activeSegments[0].w;
coreGlobals.segments[GTS3locals.alphaNumCol ].w = GTS3locals.activeSegments[1].w;
}
if ((data & DBLNK) == 0)
{
core_write_pwm_output_8b(CORE_MODOUT_SEG0 + (GTS3locals.alphaNumCol + 20) * 16 , GTS3locals.activeSegments[0].b.lo);
core_write_pwm_output_8b(CORE_MODOUT_SEG0 + (GTS3locals.alphaNumCol + 20) * 16 + 8, GTS3locals.activeSegments[0].b.hi);
core_write_pwm_output_8b(CORE_MODOUT_SEG0 + (GTS3locals.alphaNumCol ) * 16 , GTS3locals.activeSegments[1].b.lo);
core_write_pwm_output_8b(CORE_MODOUT_SEG0 + (GTS3locals.alphaNumCol ) * 16 + 8, GTS3locals.activeSegments[1].b.hi);
}
else if (GTS3locals.u4pb & ~data & DBLNK && GTS3locals.alphaNumCol < 20) { // DBlank end (negative edge)
// Non dimmed segments emulation: use the column and value defined during DBLNK
coreGlobals.segments[GTS3locals.alphaNumCol + 20].w = GTS3locals.activeSegments[0].w;
coreGlobals.segments[GTS3locals.alphaNumCol ].w = GTS3locals.activeSegments[1].w;
core_write_pwm_output_8b(CORE_MODOUT_SEG0 + (GTS3locals.alphaNumCol + 20) * 16 , GTS3locals.activeSegments[0].b.lo);
core_write_pwm_output_8b(CORE_MODOUT_SEG0 + (GTS3locals.alphaNumCol + 20) * 16 + 8, GTS3locals.activeSegments[0].b.hi);
core_write_pwm_output_8b(CORE_MODOUT_SEG0 + (GTS3locals.alphaNumCol ) * 16 , GTS3locals.activeSegments[1].b.lo);
core_write_pwm_output_8b(CORE_MODOUT_SEG0 + (GTS3locals.alphaNumCol ) * 16 + 8, GTS3locals.activeSegments[1].b.hi);
}
}
else
{ // DMD generation
else { // DMD generation
GTS3_dmdlocals[0].dstrb = (data & DSTRB) != 0;
}

Expand Down Expand Up @@ -821,25 +808,23 @@ static WRITE_HANDLER(display_control) { GTS3locals.DISPLAY_CONTROL(offset,data);
*/
static WRITE_HANDLER(alpha_display){
/* Adjust the 16 Segment Layout to match the output order expected by core.c */
if (offset & 1) // Hi byte (8..15)
{
if (offset & 1) { // Hi byte (8..15)
GTS3locals.activeSegments[offset >> 1].w &= 0x063F; // Remove bits 6..8 and 11..15
GTS3locals.activeSegments[offset >> 1].w |= ((data & 0x0F) << 11) /* 8..11 => 11..14 */
| ((data & 0x10) << 2) /* 12 => 6 */
| ((data & 0x20) << 3) /* 13 => 8 */
| ((data & 0x40) << 9) /* 14 => 15 */
| ((data & 0x80) ); /* 15 => 7 */
| ((data & 0x10) << 2) /* 12 => 6 */
| ((data & 0x20) << 3) /* 13 => 8 */
| ((data & 0x40) << 9) /* 14 => 15 */
| ((data & 0x80) ); /* 15 => 7 */
}
else // Lo byte (0..7)
{
else { // Lo byte (0..7)
GTS3locals.activeSegments[offset >> 1].w &= 0xF9C0; // Remove bits 0..5 and 9..10
GTS3locals.activeSegments[offset >> 1].w |= ((data & 0x3F) ) /* 0.. 5 => 0.. 5 */
| ((data & 0xC0) << 3); /* 6.. 7 => 9..10 */
| ((data & 0xC0) << 3); /* 6.. 7 => 9..10 */
}
if (((GTS3locals.u4pb & DBLNK) == 0) && (GTS3locals.alphaNumCol < 20)) { // This should never happen since character pattern is loaded to the latch registers while DBLNK is raised
core_write_pwm_output_8b(CORE_MODOUT_SEG0 + (GTS3locals.alphaNumCol + 20) * 16 , GTS3locals.activeSegments[0].b.lo);
core_write_pwm_output_8b(CORE_MODOUT_SEG0 + (GTS3locals.alphaNumCol + 20) * 16 + 8, GTS3locals.activeSegments[0].b.hi);
core_write_pwm_output_8b(CORE_MODOUT_SEG0 + (GTS3locals.alphaNumCol ) * 16 , GTS3locals.activeSegments[0].b.lo);
core_write_pwm_output_8b(CORE_MODOUT_SEG0 + (GTS3locals.alphaNumCol ) * 16 , GTS3locals.activeSegments[1].b.lo);
core_write_pwm_output_8b(CORE_MODOUT_SEG0 + (GTS3locals.alphaNumCol ) * 16 + 8, GTS3locals.activeSegments[1].b.hi);
}
}
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36 changes: 19 additions & 17 deletions src/wpc/wpc.c
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Original file line number Diff line number Diff line change
Expand Up @@ -762,35 +762,36 @@ WRITE_HANDLER(wpc_w) {
case WPC_ROMBANK: { /* change rom bank */
int bank = data & wpclocals.pageMask;
cpu_setbank(1, memory_region(WPC_ROMREGION)+ bank * 0x4000);
#ifdef PINMAME
/* Bank support for CODELIST */
cpu_bankid[1] = bank + ( 0x3F ^ wpclocals.pageMask );
#endif /* PINMAME */
#ifdef PINMAME
/* Bank support for CODELIST */
cpu_bankid[1] = bank + ( 0x3F ^ wpclocals.pageMask );
#endif /* PINMAME */
break;
}
case WPC_FLIPPERS: /* Flipper coils */
if ((core_gameData->gen & GENWPC_HASWPC95) == 0) {
wpclocals.solFlip &= wpclocals.nonFlipBits;
wpclocals.solFlip |= wpclocals.solFlipPulse = ~data;
#ifdef WPC_FAST_FLIP
coreGlobals.solenoids2 |= wpclocals.solFlip;
#endif
#ifdef WPC_FAST_FLIP
coreGlobals.solenoids2 |= wpclocals.solFlip;
#endif
}
break;
case WPC_FLIPPERCOIL95: /* WPC_EXTBOARD4 */
if (core_gameData->hw.gameSpecific2 == WPC_PH) { // PH: LED digits
if (data != 0xff) {
coreGlobals.segments[core_BitColToNum(0xff ^ data)].w = wpclocals.alphaSeg[core_BitColToNum(0xff ^ data)].w = core_bcd2seg7[wpc_data[WPC_EXTBOARD1]];
}
} else if (core_gameData->gen & GENWPC_HASWPC95) {
} else if (core_gameData->gen & GENWPC_HASWPC95) { // WPC_FLIPPERCOIL95
wpclocals.solFlip &= wpclocals.nonFlipBits;
wpclocals.solFlip |= wpclocals.solFlipPulse = data;
#ifdef WPC_FAST_FLIP
coreGlobals.solenoids2 |= wpclocals.solFlip;
#endif
#ifdef WPC_FAST_FLIP
coreGlobals.solenoids2 |= wpclocals.solFlip;
#endif
}
else if ((core_gameData->gen & GENWPC_HASDMD) == 0)
else if ((core_gameData->gen & GENWPC_HASDMD) == 0) // WPC_ALPHA2LO
{
static double prev; printf("WPC_ALPHA2LO %8.5fms %02x %02x\n", timer_get_time() - prev, wpc_data[WPC_ALPHAPOS], data); prev = timer_get_time();
wpclocals.alphaSeg[20+wpc_data[WPC_ALPHAPOS]].b.lo |= data;
if (options.usemodsol & (CORE_MODOUT_ENABLE_PHYSOUT_ALPHASEGS | CORE_MODOUT_FORCE_ON))
core_write_pwm_output_8b(CORE_MODOUT_SEG0 + (20 + wpc_data[WPC_ALPHAPOS]) * 2 * 8, data);
Expand Down Expand Up @@ -861,12 +862,13 @@ WRITE_HANDLER(wpc_w) {
core_write_masked_pwm_output_8b(CORE_MODOUT_SOL0 + 48, data << 2, 0xFC); // Write 50..55
core_write_masked_pwm_output_8b(CORE_MODOUT_SOL0 + 56, data >> 6, 0x03); // Write 56..57
}
else if ((core_gameData->gen & GENWPC_HASDMD) == 0)
else if ((core_gameData->gen & GENWPC_HASDMD) == 0) // WPC_ALPHAPOS
{
// Alphanumeric segment strobing change => turn off previous segment and on the ones of the new selected position
// Operation is set all segs to 0 (blanking), then strove to next column, then set segments.
// The delay between setting segments then blanking them is used to a rough PWM dimming
// Overall timing is 1ms maximum per digit over a 16ms period
static double prev; printf("WPC_ALPHAPOS %8.5fms %02x\n", timer_get_time() - prev, data); prev = timer_get_time();
if (options.usemodsol & (CORE_MODOUT_ENABLE_PHYSOUT_ALPHASEGS | CORE_MODOUT_FORCE_ON))
{
int prevIndex = CORE_MODOUT_SEG0 + wpc_data[WPC_ALPHAPOS] * 2 * 8;
Expand All @@ -881,7 +883,7 @@ WRITE_HANDLER(wpc_w) {
}
}
break; /* just save position */
case WPC_EXTBOARD2: /* WPC_ALPHA1 */
case WPC_EXTBOARD2: /* WPC_ALPHA1LO */
if (core_gameData->hw.gameSpecific2 == WPC_PH) { // PH: lamps 65 .. 128 (data is row of 2nd matrix)
core_write_pwm_output_lamp_matrix(CORE_MODOUT_LAMP0 + 64, wpc_data[WPC_LAMPCOLUMN], data, 8);
}
Expand All @@ -891,18 +893,18 @@ WRITE_HANDLER(wpc_w) {
core_write_masked_pwm_output_8b(CORE_MODOUT_SOL0 + 48, data << 2, 0xFC); // Write 50..55
core_write_masked_pwm_output_8b(CORE_MODOUT_SOL0 + 56, data >> 6, 0x03); // Write 56..57
}
else if ((core_gameData->gen & GENWPC_HASDMD) == 0)
else if ((core_gameData->gen & GENWPC_HASDMD) == 0) // WPC_ALPHA1LO
{
wpclocals.alphaSeg[wpc_data[WPC_ALPHAPOS]].b.lo |= data;
if (options.usemodsol & (CORE_MODOUT_ENABLE_PHYSOUT_ALPHASEGS | CORE_MODOUT_FORCE_ON))
core_write_pwm_output_8b(CORE_MODOUT_SEG0 + wpc_data[WPC_ALPHAPOS] * 2 * 8, data);
}
break;
case WPC_EXTBOARD3:
case WPC_EXTBOARD3: /* WPC_ALPHA1HI */
if (core_gameData->hw.gameSpecific2 == WPC_PH) { // PH: lamps 129 .. 192 (data is row of 3rd matrix)
core_write_pwm_output_lamp_matrix(CORE_MODOUT_LAMP0 + 128, wpc_data[WPC_LAMPCOLUMN], data, 8);
}
if ((core_gameData->gen & GENWPC_HASDMD) == 0)
if ((core_gameData->gen & GENWPC_HASDMD) == 0) // WPC_ALPHA1HI
{
wpclocals.alphaSeg[wpc_data[WPC_ALPHAPOS]].b.hi |= data;
core_write_pwm_output_8b(CORE_MODOUT_SEG0 + (wpc_data[WPC_ALPHAPOS] * 2 + 1) * 8, data);
Expand Down
35 changes: 19 additions & 16 deletions src/wpc/wpc.h
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Original file line number Diff line number Diff line change
Expand Up @@ -154,17 +154,18 @@ extern const core_tLCDLayout wpc_dispDMD[];
/
/ Dr. Who is the only game testing the shifter.
/------------------------------------------------------------------------------
/ A = Alpha, M = ?, F = Fliptronics, D = DCS, S = Security, 9 = WPC95
/------------------------------------------------AMFDS9-------------------------*/
/* 3fb0 .. 3fb7 - RS232 on WPC95 Audio/Video Board (used for NBA fastbreak linking and debugging) */
/* 3fb8 .. 3fbf - DMD controller board */
#define WPC_DMD_PAGE3200 (0x3fb8 - WPC_BASE) /* W: CPU access memory bank select (added with WPC-95 as discrete IC was replaced by a custom chip) */
#define WPC_DMD_PAGE3000 (0x3fb9 - WPC_BASE) /* W: CPU access memory bank select (added with WPC-95 as discrete IC was replaced by a custom chip) */
#define WPC_DMD_PAGE3600 (0x3fba - WPC_BASE) /* W: CPU access memory bank select (added with WPC-95 as discrete IC was replaced by a custom chip) */
#define WPC_DMD_PAGE3400 (0x3fbb - WPC_BASE) /* W: CPU access memory bank select (added with WPC-95 as discrete IC was replaced by a custom chip) */
#define WPC_DMD_PAGE3A00 (0x3fbc - WPC_BASE) /* W: CPU access memory bank select (HIGHPAGEWR in schematics 16.9148.1) */
#define WPC_DMD_FIRQLINE (0x3fbd - WPC_BASE) /* R: Bit7 FIRQ state W: ack DMD FIRQ and write row number to raise next FIRQ (FIRQRD/ROW_IRQ in schematics 16.9148.1) */
#define WPC_DMD_PAGE3800 (0x3fbe - WPC_BASE) /* W: CPU access memory bank select (LOWPAGEWR in schematics 16.9148.1) */
#define WPC_DMD_SHOWPAGE (0x3fbf - WPC_BASE) /* W: page to rasterize on next VBlank (DISPAGEWR in schematics 16.9148.1) */
#define WPC_DMD_PAGE3200 (0x3fb8 - WPC_BASE) /* x W: CPU access memory bank select (added with WPC-95 as discrete IC was replaced by a custom chip) */
#define WPC_DMD_PAGE3000 (0x3fb9 - WPC_BASE) /* x W: CPU access memory bank select (added with WPC-95 as discrete IC was replaced by a custom chip) */
#define WPC_DMD_PAGE3600 (0x3fba - WPC_BASE) /* x W: CPU access memory bank select (added with WPC-95 as discrete IC was replaced by a custom chip) */
#define WPC_DMD_PAGE3400 (0x3fbb - WPC_BASE) /* x W: CPU access memory bank select (added with WPC-95 as discrete IC was replaced by a custom chip) */
#define WPC_DMD_PAGE3A00 (0x3fbc - WPC_BASE) /* x W: CPU access memory bank select (HIGHPAGEWR in schematics 16.9148.1) */
#define WPC_DMD_FIRQLINE (0x3fbd - WPC_BASE) /* xxxx R: Bit7 FIRQ state W: ack DMD FIRQ and write row number to raise next FIRQ (FIRQRD/ROW_IRQ in schematics 16.9148.1) */
#define WPC_DMD_PAGE3800 (0x3fbe - WPC_BASE) /* xxxx W: CPU access memory bank select (LOWPAGEWR in schematics 16.9148.1) */
#define WPC_DMD_SHOWPAGE (0x3fbf - WPC_BASE) /* xxxx W: page to rasterize on next VBlank (DISPAGEWR in schematics 16.9148.1) */
/* 3fc0 .. 3fdf - External IO boards */
/* Printer board */
#define WPC_PRINTBUSY (0x3fc0 - WPC_BASE) /* xxxxx R: Printer ready ??? */
Expand Down Expand Up @@ -192,25 +193,27 @@ extern const core_tLCDLayout wpc_dispDMD[];
#define WPC_SOLENOID4 (0x3fe3 - WPC_BASE) /* xxxxxx W: Solenoid 9-16 */
#define WPC_LAMPROW (0x3fe4 - WPC_BASE) /* xxxxxx W: Lamp row */
#define WPC_LAMPCOLUMN (0x3fe5 - WPC_BASE) /* xxxxxx W: Lamp column enable */
#define WPC_GILAMPS (0x3fe6 - WPC_BASE) /* W: GI lights ?? */
#define WPC_GILAMPS (0x3fe6 - WPC_BASE) /* W: GI Triac driver */
#define WPC_DIPSWITCH (0x3fe7 - WPC_BASE) /* xxxxxx R: CPU board dip-switches */
#define WPC_SWCOINDOOR (0x3fe8 - WPC_BASE) /* xxxxxx W: Coin door switches */
#define WPC_SWROWREAD (0x3fe9 - WPC_BASE) /* xxxx R: Switch row read */
#define WPC_PICREAD (0x3fe9 - WPC_BASE) /* xx R: PIC data */
#define WPC_PICREAD (0x3fe9 - WPC_BASE) /* xx R: PIC data (include switch read) */
#define WPC_SWCOLSELECT (0x3fea - WPC_BASE) /* xxxx W: Switch column enable */
#define WPC_PICWRITE (0x3fea - WPC_BASE) /* xx R: PIC data */
#define WPC_PICWRITE (0x3fea - WPC_BASE) /* xx R: PIC data (include switch strobe) */
/* External board / Alphanum display / WPC95 flippers 0x3feb-0x3fef */
#define WPC_EXTBOARD1 (0x3feb - WPC_BASE) /* x W: Extension Driver Board 1 */
#define WPC_ALPHAPOS (0x3feb - WPC_BASE) /* x W: Select alphanumeric position */
#define WPC_ALPHAPOS (0x3feb - WPC_BASE) /* x W: Alphanumeric column /DIS_STROBE */
#define WPC_EXTBOARD2 (0x3fec - WPC_BASE) /* x W: Extension Driver Board 2 */
#define WPC_ALPHA1HI (0x3fec - WPC_BASE) /* x W: Display 1st row hi bits */
#define WPC_ALPHA1LO (0x3fec - WPC_BASE) /* x W: Alphanumeric 1st row lo bits /DIS_1 */
#define WPC_EXTBOARD3 (0x3fed - WPC_BASE) /* x W: Extension Driver Board 3 */
#define WPC_ALPHA1LO (0x3fed - WPC_BASE) /* x W: Display 1st row lo bits */
#define WPC_ALPHA1HI (0x3fed - WPC_BASE) /* x W: Alphanumeric 1st row hi bits /DIS_2 */
#define WPC_EXTBOARD4 (0x3fee - WPC_BASE) /* x W: Extension Driver Board 4 */
#define WPC_FLIPPERCOIL95 (0x3fee - WPC_BASE) /* x W: Flipper Solenoids */
#define WPC_ALPHA2HI (0x3fef - WPC_BASE) /* x W: Display 2nd row hi bits */
#define WPC_ALPHA2LO (0x3fee - WPC_BASE) /* x W: b 2nd row lo bits */
#define WPC_ALPHA2LO (0x3fee - WPC_BASE) /* x W: Alphanumeric 2nd row lo bits /DIS_3 */
#define WPC_EXTBOARD5 (0x3fef - WPC_BASE) /* x W: Extension Driver Board 5 */
#define WPC_FLIPPERSW95 (0x3fef - WPC_BASE) /* x R: Flipper switches */
#define WPC_ALPHA2HI (0x3fef - WPC_BASE) /* x W: Alphanumeric 2nd row hi bits /DIS_4 */
/* CPU board features 0x3ff0 - 0x3fff */
#define WPC_LED (0x3ff2 - WPC_BASE) /* xxxxxx W: CPU LED (bit 7) */
#define WPC_IRQACK (0x3ff3 - WPC_BASE) /* W: IRQ Ack ??? */
#define WPC_SHIFTADRH (0x3ff4 - WPC_BASE) /* xxxxxx RW: See above */
Expand Down

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