Add CRTC6845 VSync output, use it for GTS3 DMD (fix Teed Off timings)

src/wpc/gts3.c

@@ -878,6 +878,13 @@ static WRITE_HANDLER(dmd_display){
 	  board only latches it when DS0 is fired (so the emulation here is not perfect).
 	*/
 	//Latch DMD Data from U7
+	/*
+    CPU board - DMD communication:
+    - CPU sends data by writing bytes to to 0x2020, triggering DS0 (DMD board latch data and set IRQ to process it)
+    - DMD board acq received data by toggling PB5 pin
+    Note that the written data is latched on the CPU board on all CPU writes, not just the ones to dmd, but the dmd 
+    board only latches it when DS0 is fired (so the emulation here is not perfect).
+   */
 	GTS3_dmdlocals[0].dmd_latch = data;
 	if (offset == 0) {
 		cpu_set_irq_line(GTS3_DCPUNO, 0, HOLD_LINE);
@@ -978,9 +985,9 @@ static WRITE_HANDLER(dmd_aux) {
 static void dmd_vblank(int which) {
 	int offset = crtc6845_start_address_r(which) >> 2;
 	if (which)
-		memcpy(DMDFrames2[GTS3_dmdlocals[1].nextDMDFrame],memory_region(GTS3_MEMREG_DCPU2)+0x1000+offset,0x200);
+		memcpy(DMDFrames2[GTS3_dmdlocals[1].nextDMDFrame], memory_region(GTS3_MEMREG_DCPU2) + 0x1000 + offset, 0x200);
 	else
-		memcpy(DMDFrames[GTS3_dmdlocals[0].nextDMDFrame],memory_region(GTS3_MEMREG_DCPU1)+0x1000+offset,0x200);
+		memcpy(DMDFrames[GTS3_dmdlocals[0].nextDMDFrame], memory_region(GTS3_MEMREG_DCPU1) + 0x1000 + offset, 0x200);
 	cpu_set_nmi_line(which ? GTS3_DCPUNO2 : GTS3_DCPUNO, PULSE_LINE);
 	GTS3_dmdlocals[which].nextDMDFrame = (GTS3_dmdlocals[which].nextDMDFrame + 1) % (GTS3_dmdlocals[0].color_mode == 0 ? GTS3DMD_FRAMES_4C_a : (GTS3_dmdlocals[0].color_mode == 1 ? GTS3DMD_FRAMES_4C_b : GTS3DMD_FRAMES_5C));
 }