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fix: rename segment common cathode pin
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y5c4l3 committed Jan 23, 2024
1 parent d1b060a commit 810438c
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Showing 2 changed files with 4 additions and 4 deletions.
2 changes: 1 addition & 1 deletion Cargo.toml
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
[package]
name = "rust-hdl-bsp-step-mxo2-lpc"
version = "0.1.1"
version = "0.1.2"
edition = "2021"
authors = ["y5c4l3 <[email protected]>"]
description = "rust-hdl board support package for STEP-MXO2-LPC"
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6 changes: 3 additions & 3 deletions src/pins.rs
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@ pub const CLOCK_SPEED_12MHZ: u64 = 12_000_000;
#[derive(LogicInterface, Default)]
pub struct SegmentDisplay {
pub segments: Signal<Out, Bits<8>>,
pub enabled: Signal<Out, Bit>,
pub dimmed: Signal<Out, Bit>,
}

pub fn clock() -> Signal<In, Clock> {
Expand Down Expand Up @@ -60,15 +60,15 @@ pub fn rgb_leds() -> [Signal<Out, Bits<3>>; 2] {

pub fn segment_displays() -> [SegmentDisplay; 2] {
let mut displays = <[SegmentDisplay; 2]>::default();
displays[0].enabled.add_location(0, "C9");
displays[0].dimmed.add_location(0, "C9");
let locs = ["A10", "C11", "F2", "E1", "E2", "A9", "B9", "F1"];
for (i, loc) in locs.iter().enumerate() {
displays[0].segments.add_location(i, loc);
displays[0]
.segments
.add_signal_type(i, SignalType::LowVoltageCMOS_3v3);
}
displays[1].enabled.add_location(0, "A12");
displays[1].dimmed.add_location(0, "A12");
let locs = ["C12", "B14", "J1", "H1", "H2", "B12", "A11", "K1"];
for (i, loc) in locs.iter().enumerate() {
displays[1].segments.add_location(i, loc);
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