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Issues: ymherklotz/verismith
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verismith never generates simple 'if' statements - only 'if/else' statements
enhancement
New feature or request
#94
opened Apr 26, 2023 by
yurivict
verismith generates mismatching Verilog assign statements
bug
Something isn't working
#90
opened Apr 11, 2023 by
yurivict
verismith doesn't generate assign statements with concatenation and bit selectors in the LHS
enhancement
New feature or request
#89
opened Apr 11, 2023 by
yurivict
Shuffle signal and module instantiation
bug
Something isn't working
#81
opened Nov 25, 2022 by
dwRchyngqxs
Add SystemVerilog parsers found in sv-tests?
enhancement
New feature or request
#77
opened Oct 19, 2020 by
mithro
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