soc/mediatek: HWMv2 normalization

There is resistance to having the top-level board/SOC in this scheme be an "audio DSP" (the real devices are integrated application processors running Linux with GPUs, etc...). So effect a big rename a-la HWMv2: + Board and SOC get the full product name and lose their "_adsp" suffix + "adsp" becomes a CPU Cluster underneath the SOC + All the various kconfigs get renamed accordingly The only user-visible impact is that the "board-only" name disappears, and you have to specify e.g. "mt8196/mt8196/adsp" to west (though you can elide the duplicate SOC name as use "mt8196//adsp" if desired). Signed-off-by: Andy Ross <[email protected]>
zephyrproject-rtos · Nov 15, 2024 · 19d548e · 19d548e
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diff --git a/boards/mediatek/index.rst b/boards/mediatek/index.rst
@@ -67,12 +67,12 @@ my mt8186 device named "steelix":
 
 .. code-block:: console
 
-   user@dev_host:~$ west build -b mt8186_adsp samples/hello_world
+   user@dev_host:~$ west build -b mt8186//adsp samples/hello_world
    ...
    ... # build output
    ...
    user@dev_host:~$ scp build/zephyr/zephyr.img root@steelix:
-   user@dev_host:~$ scp soc/mediatek/mtk_adsp/mtk_adsp_load.py root@steelix:
+   user@dev_host:~$ scp soc/mediatek/mt8xxx/mtk_adsp_load.py root@steelix:
    user@dev_host:~$ ssh steelix
 
    root@steelix:~ # ./mtk_adsp_load.py load zephyr.img
@@ -94,7 +94,7 @@ Toolchains
 **********
 
 The MT8195 toolchain is already part of the Zephyr SDK, so builds for
-the ``mt8195_adsp`` board should work out of the box simply following
+the ``mt8195//adsp`` board should work out of the box simply following
 the generic Zephyr build instructions in the Getting Started guide.
 
 The MT8186 toolchain is not, and given the proliferation of Xtensa

diff --git a/.../mediatek/mt8186_adsp/Kconfig.mt8186_adsp → boards/mediatek/mt8186/Kconfig.mt8186 b/.../mediatek/mt8186_adsp/Kconfig.mt8186_adsp → boards/mediatek/mt8186/Kconfig.mt8186
@@ -1,5 +1,5 @@
 # Copyright 2024 The ChromiumOS Authors
 # SPDX-License-Identifier: Apache-2.0
 
-config BOARD_MT8186_ADSP
-	select SOC_MT8186_ADSP
+config BOARD_MT8186
+	select SOC_MT8186
diff --git a/boards/mediatek/mt8186/board.yml b/boards/mediatek/mt8186/board.yml
@@ -0,0 +1,5 @@
+boards:
+  - name: mt8186
+    vendor: mediatek
+    socs:
+      - name: mt8186
diff --git a/boards/mediatek/mt8186_adsp/mt8186_adsp.dts → boards/mediatek/mt8186/mt8186_adsp.dts b/boards/mediatek/mt8186_adsp/mt8186_adsp.dts → boards/mediatek/mt8186/mt8186_adsp.dts
diff --git a/boards/mediatek/mt8186_adsp/board.yml b/boards/mediatek/mt8186_adsp/board.yml
diff --git a/.../mediatek/mt8188_adsp/Kconfig.mt8188_adsp → boards/mediatek/mt8188/Kconfig.mt8188 b/.../mediatek/mt8188_adsp/Kconfig.mt8188_adsp → boards/mediatek/mt8188/Kconfig.mt8188
@@ -1,5 +1,5 @@
 # Copyright 2024 The ChromiumOS Authors
 # SPDX-License-Identifier: Apache-2.0
 
-config BOARD_MT8188_ADSP
-	select SOC_MT8188_ADSP
+config BOARD_MT8188
+	select SOC_MT8188
diff --git a/boards/mediatek/mt8188/board.yml b/boards/mediatek/mt8188/board.yml
@@ -0,0 +1,5 @@
+boards:
+  - name: mt8188
+    vendor: mediatek
+    socs:
+      - name: mt8188
diff --git a/boards/mediatek/mt8188_adsp/mt8188_adsp.dts → boards/mediatek/mt8188/mt8188_adsp.dts b/boards/mediatek/mt8188_adsp/mt8188_adsp.dts → boards/mediatek/mt8188/mt8188_adsp.dts
diff --git a/boards/mediatek/mt8188_adsp/board.yml b/boards/mediatek/mt8188_adsp/board.yml
diff --git a/.../mediatek/mt8195_adsp/Kconfig.mt8195_adsp → boards/mediatek/mt8195/Kconfig.mt8195 b/.../mediatek/mt8195_adsp/Kconfig.mt8195_adsp → boards/mediatek/mt8195/Kconfig.mt8195
@@ -1,7 +1,7 @@
 # Copyright 2023 The ChromiumOS Authors
 # SPDX-License-Identifier: Apache-2.0
 
-config BOARD_MT8195_ADSP
-	select SOC_MT8195_ADSP
+config BOARD_MT8195
+	select SOC_MT8195
 	help
 	  Board with Mediatek MT8195 Audio DSP
diff --git a/boards/mediatek/mt8195_adsp/board.yml → boards/mediatek/mt8195/board.yml b/boards/mediatek/mt8195_adsp/board.yml → boards/mediatek/mt8195/board.yml
@@ -1,6 +1,6 @@
 boards:
-  - name: mt8195_adsp
+  - name: mt8195
     full_name: MT8195 ADSP
     vendor: mediatek
     socs:
-      - name: mt8195_adsp
+      - name: mt8195
diff --git a/boards/mediatek/mt8195_adsp/mt8195_adsp.dts → boards/mediatek/mt8195/mt8195_adsp.dts b/boards/mediatek/mt8195_adsp/mt8195_adsp.dts → boards/mediatek/mt8195/mt8195_adsp.dts
diff --git a/.../mediatek/mt8196_adsp/Kconfig.mt8196_adsp → boards/mediatek/mt8196/Kconfig.mt8196 b/.../mediatek/mt8196_adsp/Kconfig.mt8196_adsp → boards/mediatek/mt8196/Kconfig.mt8196
@@ -1,5 +1,5 @@
 # Copyright 2024 The ChromiumOS Authors
 # SPDX-License-Identifier: Apache-2.0
 
-config BOARD_MT8196_ADSP
-	select SOC_MT8196_ADSP
+config BOARD_MT8196
+	select SOC_MT8196
diff --git a/boards/mediatek/mt8196/board.yml b/boards/mediatek/mt8196/board.yml
@@ -0,0 +1,5 @@
+boards:
+  - name: mt8196
+    vendor: mediatek
+    socs:
+      - name: mt8196
diff --git a/boards/mediatek/mt8196_adsp/mt8196_adsp.dts → boards/mediatek/mt8196/mt8196_adsp.dts b/boards/mediatek/mt8196_adsp/mt8196_adsp.dts → boards/mediatek/mt8196/mt8196_adsp.dts
diff --git a/boards/mediatek/mt8196_adsp/board.yml b/boards/mediatek/mt8196_adsp/board.yml
diff --git a/drivers/timer/mtk_adsp_timer.c b/drivers/timer/mtk_adsp_timer.c
@@ -56,7 +56,7 @@ struct mtk_ostimer64 {
 #define OSTIMER_CON_CLKSRC_BCLK 0x20 /*  CPU speed, 720 MHz */
 #define OSTIMER_CON_CLKSRC_PCLK 0x30 /*  ~312 MHz experimentally */
 
-#ifndef CONFIG_SOC_MT8196_ADSP
+#ifndef CONFIG_SOC_MT8196
 #define OSTIMER_IRQ_ACK_ENABLE BIT(4) /*  read = status, write = enable */
 #define OSTIMER_IRQ_ACK_CLEAR  BIT(5)
 #else

diff --git a/soc/mediatek/mtk_adsp/CMakeLists.txt → soc/mediatek/mt8xxx/CMakeLists.txt b/soc/mediatek/mtk_adsp/CMakeLists.txt → soc/mediatek/mt8xxx/CMakeLists.txt
@@ -3,7 +3,7 @@
 
 zephyr_library_sources(soc.c irq.c mbox.c)
 
-zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_MT8195_ADSP cpuclk.c)
+zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_MT8195 cpuclk.c)
 
 set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/${CONFIG_SOC}/linker.ld CACHE INTERNAL "")
 

diff --git a/soc/mediatek/mtk_adsp/Kconfig → soc/mediatek/mt8xxx/Kconfig b/soc/mediatek/mtk_adsp/Kconfig → soc/mediatek/mt8xxx/Kconfig
@@ -1,6 +1,6 @@
 # Copyright 2024 The ChromiumOS Authors
 # SPDX-License-Identifier: Apache-2.0
 
-config SOC_FAMILY_MTK_ADSP
+config SOC_FAMILY_MTK
 	select XTENSA
 	select XTENSA_GEN_HANDLERS
diff --git a/soc/mediatek/mtk_adsp/Kconfig.defconfig → soc/mediatek/mt8xxx/Kconfig.defconfig b/soc/mediatek/mtk_adsp/Kconfig.defconfig → soc/mediatek/mt8xxx/Kconfig.defconfig
@@ -3,7 +3,7 @@
 
 orsource "*/Kconfig.defconfig"
 
-if SOC_FAMILY_MTK_ADSP
+if SOC_FAMILY_MTK
 
 config SOC_FAMILY
 	default "mtk_adsp"
@@ -31,7 +31,7 @@ config 2ND_LVL_ISR_TBL_OFFSET
 # can't reliably do this.  Unselect so the tests don't try to exercise
 # it.
 config IRQ_OFFLOAD_NESTED
-	default n if SOC_SERIES_MT818X_ADSP
+	default n if SOC_SERIES_MT818X
 	default y
 
 config MTK_ADSP_TIMER
@@ -62,8 +62,8 @@ config XTENSA_HAL
 	default y
 
 config SOC_TOOLCHAIN_NAME
-	default "mtk_mt8195_adsp" if SOC_SERIES_MT8195_ADSP
-	default "mtk_mt818x_adsp" if SOC_SERIES_MT818X_ADSP
+	default "mtk_mt8195_adsp" if SOC_SERIES_MT8195
+	default "mtk_mt818x_adsp" if SOC_SERIES_MT818X
 
 config XTENSA_RESET_VECTOR
 	default n
@@ -84,4 +84,4 @@ config GEN_SW_ISR_TABLE
 config GEN_IRQ_VECTOR_TABLE
 	default n
 
-endif # SOC_FAMILY_MTK_ADSP
+endif # SOC_FAMILY_MTK
diff --git a/soc/mediatek/mt8xxx/Kconfig.soc b/soc/mediatek/mt8xxx/Kconfig.soc
@@ -0,0 +1,45 @@
+# Copyright 2024 The ChromiumOS Authors
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_FAMILY_MTK
+	bool
+
+config SOC_SERIES_MT8195
+	bool
+	select SOC_FAMILY_MTK
+	help
+	  Mediatek MT8195 Audio DSP
+
+config SOC_SERIES_MT818X
+	bool
+	select SOC_FAMILY_MTK
+	help
+	  Mediatek MT818x Audio DSPs
+
+config SOC_SERIES_MT8196
+	bool
+	select SOC_FAMILY_MTK
+	help
+	  Mediatek MT8196 Audio DSPs
+
+config SOC_MT8195
+	bool
+	select SOC_SERIES_MT8195
+
+config SOC_MT8186
+	bool
+	select SOC_SERIES_MT818X
+
+config SOC_MT8188
+	bool
+	select SOC_SERIES_MT818X
+
+config SOC_MT8196
+	bool
+	select SOC_SERIES_MT8196
+
+config SOC
+	default "mt8195" if SOC_MT8195
+	default "mt8186" if SOC_MT8186
+	default "mt8188" if SOC_MT8188
+	default "mt8196" if SOC_MT8196
diff --git a/soc/mediatek/mtk_adsp/cpuclk.c → soc/mediatek/mt8xxx/cpuclk.c b/soc/mediatek/mtk_adsp/cpuclk.c → soc/mediatek/mt8xxx/cpuclk.c
diff --git a/soc/mediatek/mtk_adsp/gen_img.py → soc/mediatek/mt8xxx/gen_img.py b/soc/mediatek/mtk_adsp/gen_img.py → soc/mediatek/mt8xxx/gen_img.py
diff --git a/soc/mediatek/mtk_adsp/irq.c → soc/mediatek/mt8xxx/irq.c b/soc/mediatek/mtk_adsp/irq.c → soc/mediatek/mt8xxx/irq.c
@@ -16,7 +16,7 @@ void intc_mtk_adsp_set_enable(const struct device *dev, int irq, bool val);
  */
 static const struct device *irq_dev(unsigned int *irq_inout)
 {
-#ifdef CONFIG_SOC_SERIES_MT8195_ADSP
+#ifdef CONFIG_SOC_SERIES_MT8195
 	/* Controller 0 is on Xtensa vector 1, controller 1 on vector 23. */
 	if ((*irq_inout & 0xff) == 1) {
 		*irq_inout >>= 8;
@@ -25,7 +25,7 @@ static const struct device *irq_dev(unsigned int *irq_inout)
 	__ASSERT_NO_MSG((*irq_inout & 0xff) == 23);
 	*irq_inout = (*irq_inout >> 8) - 1;
 	return DEVICE_DT_GET(DT_INST(1, mediatek_adsp_intc));
-#elif defined(CONFIG_SOC_SERIES_MT8196_ADSP)
+#elif defined(CONFIG_SOC_SERIES_MT8196)
 	/* Two subcontrollers on core IRQs 1 and 2 */
 	uint32_t lvl1 = *irq_inout & 0xff;
 

diff --git a/soc/mediatek/mtk_adsp/linker.ld → soc/mediatek/mt8xxx/linker.ld b/soc/mediatek/mtk_adsp/linker.ld → soc/mediatek/mt8xxx/linker.ld
diff --git a/soc/mediatek/mtk_adsp/mbox.c → soc/mediatek/mt8xxx/mbox.c b/soc/mediatek/mtk_adsp/mbox.c → soc/mediatek/mt8xxx/mbox.c
@@ -40,7 +40,7 @@
  */
 
 struct mtk_mbox {
-#ifdef SOC_SERIES_MT8195_ADSP
+#ifdef SOC_SERIES_MT8195
 	uint32_t in_cmd;
 	uint32_t in_cmd_clr;
 	uint32_t in_msg[5];

diff --git a/...ek/mtk_adsp/mt8186_adsp/Kconfig.defconfig → soc/mediatek/mt8xxx/mt8186/Kconfig.defconfig b/...ek/mtk_adsp/mt8186_adsp/Kconfig.defconfig → soc/mediatek/mt8xxx/mt8186/Kconfig.defconfig
@@ -1,7 +1,7 @@
 # Copyright 2024 The ChromiumOS Authors
 # SPDX-License-Identifier: Apache-2.0
 
-if SOC_MT8186_ADSP
+if SOC_MT8186
 
 # FIXME: move this to 818x series code to share w/8188
 config NUM_2ND_LEVEL_AGGREGATORS

diff --git a/soc/mediatek/mtk_adsp/mt8186_adsp/linker.ld → soc/mediatek/mt8xxx/mt8186/linker.ld b/soc/mediatek/mtk_adsp/mt8186_adsp/linker.ld → soc/mediatek/mt8xxx/mt8186/linker.ld
diff --git a/soc/mediatek/mt8xxx/mt8186/soc.h b/soc/mediatek/mt8xxx/mt8186/soc.h
@@ -0,0 +1,10 @@
+/* Copyright 2024 The ChromiumOS Authors
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_SOC_MT8186_SOC_H
+#define ZEPHYR_SOC_MT8186_SOC_H
+
+#include "../soc.h"
+
+#endif /* ZEPHYR_SOC_MT8186_SOC_H */
diff --git a/...ek/mtk_adsp/mt8188_adsp/Kconfig.defconfig → soc/mediatek/mt8xxx/mt8188/Kconfig.defconfig b/...ek/mtk_adsp/mt8188_adsp/Kconfig.defconfig → soc/mediatek/mt8xxx/mt8188/Kconfig.defconfig
@@ -1,7 +1,7 @@
 # Copyright 2024 The ChromiumOS Authors
 # SPDX-License-Identifier: Apache-2.0
 
-if SOC_MT8188_ADSP
+if SOC_MT8188
 
 config NUM_2ND_LEVEL_AGGREGATORS
 	default 1

diff --git a/soc/mediatek/mtk_adsp/mt8188_adsp/linker.ld → soc/mediatek/mt8xxx/mt8188/linker.ld b/soc/mediatek/mtk_adsp/mt8188_adsp/linker.ld → soc/mediatek/mt8xxx/mt8188/linker.ld
diff --git a/soc/mediatek/mt8xxx/mt8188/soc.h b/soc/mediatek/mt8xxx/mt8188/soc.h
@@ -0,0 +1,10 @@
+/* Copyright 2024 The ChromiumOS Authors
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_SOC_MT8188_SOC_H
+#define ZEPHYR_SOC_MT8188_SOC_H
+
+#include "../soc.h"
+
+#endif /* ZEPHYR_SOC_MT8188_SOC_H */
diff --git a/...ek/mtk_adsp/mt8195_adsp/Kconfig.defconfig → soc/mediatek/mt8xxx/mt8195/Kconfig.defconfig b/...ek/mtk_adsp/mt8195_adsp/Kconfig.defconfig → soc/mediatek/mt8xxx/mt8195/Kconfig.defconfig
@@ -1,7 +1,7 @@
 # Copyright 2023 The ChromiumOS Authors
 # SPDX-License-Identifier: Apache-2.0
 
-if SOC_SERIES_MT8195_ADSP
+if SOC_SERIES_MT8195
 
 config NUM_2ND_LEVEL_AGGREGATORS
 	default 2
@@ -10,4 +10,4 @@ config 2ND_LVL_INTR_00_OFFSET
 config 2ND_LVL_INTR_01_OFFSET
 	default 23
 
-endif # SOC_SERIES_MT8195_ADSP
+endif # SOC_SERIES_MT8195
diff --git a/soc/mediatek/mtk_adsp/mt8195_adsp/linker.ld → soc/mediatek/mt8xxx/mt8195/linker.ld b/soc/mediatek/mtk_adsp/mt8195_adsp/linker.ld → soc/mediatek/mt8xxx/mt8195/linker.ld
diff --git a/soc/mediatek/mt8xxx/mt8195/soc.h b/soc/mediatek/mt8xxx/mt8195/soc.h
@@ -0,0 +1,10 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_SOC_MT8195_SOC_H
+#define ZEPHYR_SOC_MT8195_SOC_H
+
+#include "../soc.h"
+
+#endif /* ZEPHYR_SOC_MT8195_SOC_H */
diff --git a/...ek/mtk_adsp/mt8196_adsp/Kconfig.defconfig → soc/mediatek/mt8xxx/mt8196/Kconfig.defconfig b/...ek/mtk_adsp/mt8196_adsp/Kconfig.defconfig → soc/mediatek/mt8xxx/mt8196/Kconfig.defconfig
@@ -1,7 +1,7 @@
 # Copyright 2024 The ChromiumOS Authors
 # SPDX-License-Identifier: Apache-2.0
 
-if SOC_MT8196_ADSP
+if SOC_MT8196
 
 config LEGACY_MULTI_LEVEL_TABLE_GENERATION
 	default n

diff --git a/soc/mediatek/mtk_adsp/mt8196_adsp/linker.ld → soc/mediatek/mt8xxx/mt8196/linker.ld b/soc/mediatek/mtk_adsp/mt8196_adsp/linker.ld → soc/mediatek/mt8xxx/mt8196/linker.ld
diff --git a/soc/mediatek/mt8xxx/mt8196/soc.h b/soc/mediatek/mt8xxx/mt8196/soc.h
@@ -0,0 +1,10 @@
+/* Copyright 2024 The ChromiumOS Authors
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_SOC_MT8196_SOC_H
+#define ZEPHYR_SOC_MT8196_SOC_H
+
+#include "../soc.h"
+
+#endif /* ZEPHYR_SOC_MT8196_SOC_H */
diff --git a/soc/mediatek/mtk_adsp/mtk_adsp_load.py → soc/mediatek/mt8xxx/mtk_adsp_load.py b/soc/mediatek/mtk_adsp/mtk_adsp_load.py → soc/mediatek/mt8xxx/mtk_adsp_load.py
diff --git a/soc/mediatek/mtk_adsp/soc.c → soc/mediatek/mt8xxx/soc.c b/soc/mediatek/mtk_adsp/soc.c → soc/mediatek/mt8xxx/soc.c
@@ -19,7 +19,7 @@ extern char _mtk_adsp_dram_end[];
 #define DRAM_SIZE  DT_REG_SIZE(DT_NODELABEL(dram0))
 #define DRAM_END   (DRAM_START + DRAM_SIZE)
 
-#ifdef CONFIG_SOC_MT8196_ADSP
+#ifdef CONFIG_SOC_MT8196
 #define INIT_STACK "0x90400000"
 #define LOG_BASE   0x90580000
 #define LOG_LEN    0x80000
@@ -159,7 +159,7 @@ void c_boot(void)
 	 */
 	__asm__ volatile("wsr %0, VECBASE; rsync" :: "r"(&z_xtensa_vecbase));
 
-#ifdef CONFIG_SOC_SERIES_MT8195_ADSP
+#ifdef CONFIG_SOC_SERIES_MT8195
 	mtk_adsp_cpu_freq_init();
 #endif
 

diff --git a/soc/mediatek/mtk_adsp/soc.h → soc/mediatek/mt8xxx/soc.h b/soc/mediatek/mtk_adsp/soc.h → soc/mediatek/mt8xxx/soc.h
@@ -2,8 +2,8 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#ifndef ZEPHYR_SOC_MTK_ADSP_SOC_H
-#define ZEPHYR_SOC_MTK_ADSP_SOC_H
+#ifndef ZEPHYR_SOC_MTK_SOC_H
+#define ZEPHYR_SOC_MTK_SOC_H
 
 #include <zephyr/device.h>
 
@@ -26,4 +26,4 @@ void mtk_adsp_mbox_set_handler(const struct device *mbox, uint32_t chan,
 /* Signal an interrupt on the specified channel for the other side */
 void mtk_adsp_mbox_signal(const struct device *mbox, uint32_t chan);
 
-#endif /* ZEPHYR_SOC_MTK_ADSP_SOC_H */
+#endif /* ZEPHYR_SOC_MTK_SOC_H */
diff --git a/soc/mediatek/mt8xxx/soc.yml b/soc/mediatek/mt8xxx/soc.yml
@@ -0,0 +1,21 @@
+family:
+  - name: mt8xxx
+    series:
+      - name: mt8195
+        socs:
+          - name: mt8195
+            cpuclusters:
+              - name: adsp
+      - name: mt818x
+        socs:
+          - name: mt8186
+            cpuclusters:
+              - name: adsp
+          - name: mt8188
+            cpuclusters:
+              - name: adsp
+      - name: mt8196
+        socs:
+          - name: mt8196
+            cpuclusters:
+              - name: adsp