The tool and instruction is borrow from the official riscv-tests repo.
Follow the chipyard setup guide in another repo.
cd case_generation
python3 test_case_generation.py
cd ../isa/rv64ui
make
- Use
simple.S
as a skeleton. Thw testcode can be write at the section betweenRVTEST_CODE_BEGIN
andRVTEST_PASS
.
RVTEST_CODE_BEGIN
# Place to insert custom test code.
RVTEST_PASS
- Use the following riscv gcc commad to compile program
riscv64-unknown-elf-gcc -march=rv64g -mabi=lp64 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -T link.ld -o simple simple.S
We get binary simple
.
- We can use riscv binary dump to inspect the binary
riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.text.init --section=.data simple