Overhaul Linter Handling of Black-boxed Verilog Models

.github/scripts/variables_documentation.py

@@ -102,6 +102,9 @@
 VCHECK_OUTPUT
 VDD_NET
 WRITE_VIEWS_NO_GLOBAL_CONNECT
+YOSYS_IN
+YOSYS_OUT
+YOSYS_DEFINES
 TECH_METAL_LAYERS
 LIB_SYNTH_COMPLETE
 LIB_SYNTH_COMPLETE_NO_PG

configuration/checkers.tcl

@@ -18,7 +18,7 @@ set ::env(QUIT_ON_UNMAPPED_CELLS) 1
 set ::env(QUIT_ON_SYNTH_CHECKS) 1
 set ::env(SYNTH_CHECKS_ALLOW_TRISTATE) 1
 set ::env(LINTER_RELATIVE_INCLUDES) 1
-set ::env(LINTER_INCLUDE_PDK_MODELS) 0
+set ::env(LINTER_INCLUDE_PDK_MODELS) 1
 set ::env(QUIT_ON_LINTER_WARNINGS) 0
 set ::env(QUIT_ON_LINTER_ERRORS) 1
 

scripts/tcl_commands/synthesis.tcl

@@ -243,29 +243,68 @@ proc logic_equiv_check {args} {
     exec echo "[TIMER::get_runtime]" | python3 $::env(SCRIPTS_DIR)/write_runtime.py "logic equivalence check - yosys"
 }
 
+
+proc generate_blackbox_verilog {inputs output {defines ""}} {
+    set output_files ""
+    set defines_flag ""
+    set ::env(YOSYS_IN) $inputs
+    set ::env(YOSYS_OUT) $output
+    if { $defines != "" } {
+        set ::env(YOSYS_DEFINES) $defines
+    }
+    try_exec yosys -c $::env(SCRIPTS_DIR)/yosys/blackbox.tcl
+    puts_info "Generated blackbox verilog ($output) from ($inputs)"
+}
+
+
 proc run_verilator {} {
-    set verilator_verified_pdks "sky130A sky130B"
-    set verilator_verified_scl "sky130_fd_sc_hd"
-    set includes ""
-    if { [string match *$::env(PDK)* $verilator_verified_pdks] == 0 || \
-        [string match *$::env(STD_CELL_LIBRARY)* $verilator_verified_scl] == 0} {
-        puts_warn "PDK '$::env(PDK)', SCL '$::env(STD_CELL_LIBRARY)' will generate errors with instantiated stdcells in the design."
-        puts_warn "Either disable QUIT_ON_LINTER_ERRORS or remove the instantiated cells."
-    } else {
-        set pdk_verilog_models [glob $::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY_OPT)/verilog/*.v]
-        foreach model $pdk_verilog_models {
-            set includes "$includes $model"
-        }
+    set pdk_model_blackbox ""
+    if { $::env(PDK) == "sky130A" ||$::env(PDK) == "sky130B" } {
+        set pdk_model "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/verilog/$::env(STD_CELL_LIBRARY)__blackbox.v"
+        set output_file "$::env(synthesis_tmpfiles)/[file rootname [file tail $pdk_model]]-bb.v"
+        generate_blackbox_verilog $pdk_model $output_file
+
+        exec echo "\n/* verilator lint_off UNDRIVEN */\n" | cat - $output_file > $output_file.tmp
+        file rename -force $output_file.tmp $output_file
+        exec echo "\n/* verilator lint_off UNUSEDSIGNAL */\n" | cat - $output_file > $output_file.tmp
+        file rename -force $output_file.tmp $output_file
+        exec echo "\n/* verilator lint_on UNUSEDSIGNAL */\n" >> $output_file
+        exec echo "\n/* verilator lint_on UNDRIVEN */\n" >> $output_file
+
+        set pdk_model_blackbox "$pdk_model_blackbox $output_file"
+    }
+    if { ($::env(PDK) == "gf180mcuC" || $::env(PDK) == "gf180mcuA" || $::env(PDK) == "gf180mcuB") && \
+        ($::env(STD_CELL_LIBRARY) == "gf180mcu_fd_sc_mcu7t5v0" || $::env(STD_CELL_LIBRARY) == "gf180mcu_fd_sc_mcu9t5v0")} {
+        set pdk_model_original "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/verilog/$::env(STD_CELL_LIBRARY).v"
+        set pdk_model_patched "$::env(synthesis_tmpfiles)/[file rootname [file tail $pdk_model_original]]-patched.v"
+        # remove not yosys friendly lines similar to "abc(x, y, z);" or "abc(x, y) bbb(z, f);"
+        exec bash -c "sed -E '/^\\s+\\S+\\s*\\(.*\\).*;.*/d' $pdk_model_original > $pdk_model_patched"
+        set output_file "$::env(synthesis_tmpfiles)/[file rootname [file tail $pdk_model_original]]-bb.v"
+        generate_blackbox_verilog $pdk_model_patched $output_file FUNCTIONAL
+
+        exec echo "\n/* verilator lint_off UNDRIVEN */\n" | cat - $output_file > $output_file.tmp
+        file rename -force $output_file.tmp $output_file
+        exec echo "\n/* verilator lint_off UNUSEDSIGNAL */\n" | cat - $output_file > $output_file.tmp
+        file rename -force $output_file.tmp $output_file
+        exec echo "\n/* verilator lint_on UNUSEDSIGNAL */\n" >> $output_file
+        exec echo "\n/* verilator lint_on UNDRIVEN */\n" >> $output_file
+
+        set pdk_model_blackbox "$pdk_model_blackbox $output_file"
     }
     set log $::env(synthesis_logs)/linter.log
-    puts_info "Running linter (Verilator) (log: [relpath . $log])..."
     set arg_list [list]
     if { $::env(LINTER_INCLUDE_PDK_MODELS) } {
-        lappend arg_list {*}$includes
+        lappend arg_list {*}$pdk_model_blackbox
     }
     lappend arg_list {*}$::env(VERILOG_FILES)
     if { [info exists ::env(VERILOG_FILES_BLACKBOX)] } {
-        lappend arg_list {*}$::env(VERILOG_FILES_BLACKBOX)
+        set output_file "$::env(synthesis_tmpfiles)/bb.v"
+        if { [info exists ::env(LINTER_DEFINES)] } {
+            generate_blackbox_verilog $::env(VERILOG_FILES_BLACKBOX) $output_file "$::env(LINTER_DEFINES)"
+        } else {
+            generate_blackbox_verilog $::env(VERILOG_FILES_BLACKBOX) $output_file
+        }
+        lappend arg_list {*}$output_file
     }
     lappend arg_list -Wno-fatal
     if { $::env(LINTER_RELATIVE_INCLUDES) } {
@@ -284,6 +323,7 @@ proc run_verilator {} {
     }
     lappend arg_list {*}$defines
 
+    puts_info "Running linter (Verilator) (log: [relpath . $log])..."
     set arg "|& tee $log $::env(TERMINAL_OUTPUT)"
     lappend arg_list {*}$arg
     try_exec bash -c "verilator \

scripts/yosys/blackbox.tcl

@@ -0,0 +1,24 @@
+# Copyright 2023 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+yosys -import
+foreach input $::env(YOSYS_IN) {
+    if { [info exists ::env(YOSYS_DEFINES)] } {
+        read_verilog -lib -D$::env(YOSYS_DEFINES) $input
+    } else {
+        read_verilog -lib $input
+    }
+}
+blackbox *
+write_verilog -noattr -noexpr -nohex -nodec -defparam -blackboxes $::env(YOSYS_OUT)