MIPS-architecture

MIPS architecture implemented in Verilog.

Name		Name	Last commit message	Last commit date
Latest commit History 5 Commits
ALU.v		ALU.v
ALU_test.v		ALU_test.v
ALUtest.v		ALUtest.v
EX_MEM_reg.v		EX_MEM_reg.v
EX_MEM_test.v		EX_MEM_test.v
ID_EX_TB.v		ID_EX_TB.v
ID_EX_reg.v		ID_EX_reg.v
IF_ID_regs.v		IF_ID_regs.v
IF_ID_test.v		IF_ID_test.v
IM_Test.v		IM_Test.v
Instruction_Memory.v		Instruction_Memory.v
Instruction_mem_Test.v		Instruction_mem_Test.v
MEM_WB_reg.v		MEM_WB_reg.v
MEM_WB_test.v		MEM_WB_test.v
MIPS.v		MIPS.v
MUX_2x1_32bit.v		MUX_2x1_32bit.v
README.md		README.md
alu_TB.v		alu_TB.v
alu_control.v		alu_control.v
alu_control_test.v		alu_control_test.v
cache.v		cache.v
cacheTest.v		cacheTest.v
cache_test.v		cache_test.v
cache_testing.v		cache_testing.v
control_unit.v		control_unit.v
control_unit_test.v		control_unit_test.v
data_memory.v		data_memory.v
data_memory_test.v		data_memory_test.v
decodeTest.v		decodeTest.v
decode_module.v		decode_module.v
decode_test.v		decode_test.v
editedpc.v		editedpc.v
execute_TB.v		execute_TB.v
execute_module.v		execute_module.v
execute_test.v		execute_test.v
fetch_module.v		fetch_module.v
fetch_module_test.v		fetch_module_test.v
fetchtest.v		fetchtest.v
fetchtesting.v		fetchtesting.v
inst-mem.v		inst-mem.v
mux_2x1_test.v		mux_2x1_test.v
reg_file.v		reg_file.v
reg_file_test.v		reg_file_test.v
sign_extend.v		sign_extend.v
sign_extend_test.v		sign_extend_test.v
write_back.v		write_back.v
write_back_test.v		write_back_test.v

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