Reintegrate main -> dev-public #238
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Rev 0p8 release
Merge dev-public into dev-integrate
Merge dev-integrate to main
…eripherals (#92) Signed-off-by: Maciej Kurc <[email protected]>
Signed-off-by: Maciej Kurc <[email protected]>
* Updating verilator to 5.010 * Removing -WnoImplicit and fixing the lint warnings * Update references to Verilator version
* Moving all prim_* -> caliptra_prim_* * Mass replace of prim -> caliptra_prim inside of source files * fix paths in compile lists * Adding caliptra_prim_cdc_rand_delay.sv * Renaming SIMULATION -> CALIPTRA_SIMULATION define * Uniquify all defines with CALIPTRA_ prefix * Minor fixes to file lists and updates for verilator 5.010
…ing (#39) * Removing prim_dom_and_2share since it's not used in the design - Cleaned up elab error in prim_sparse_fsm where there was an iterator over an enum, but the default type was logic. * Modifying compile.yml dependencies so each module target can elaborate Specifically targetting OT related IPs in this commit. * Moving FW_NUM_DWORDS declaration and adding wire nettype to tb_services * Adding prim_sparse_fsm_pkg to caliptra_top_tb.vf * Fixes for testing in vcs Match ahb timing seen at the ip level. This was changed for spi_host, but not changed for csrng/entropy_src. * Add missing prim_sparse_fsm_pkg to various vf files * Adding libs dependencies to enable package elaboration * Fix uart ifdef * Adding caliptra_prim_sparse_fsm_pkg for elab * Fix /prim_generic/->/caliptra_prim_generic/ replacements
Merge main into dev-msft
Signed-off-by: Maciej Kurc <[email protected]>
… updates. Updated implementation to remove warnings causing build failures, as well as updates to expected behavior for a few registers. Related work items: #470331
Predictor logic for SHA accelerator registers Handles checking for valid user, acquiring lock and setting user field, and soc has lock field Related work items: #471827
…itions and mbox_csr fix Update mbox CSR register model (in predictor) using delay jobs to match cycle-to-cycle the hardware behavior to resolve race conditions that arise in some edge cases. Give hwclr (due to force unlock) precedence over SW bus-write to resolve contention issue Related work items: #471301, #471788
Adding ROM and Firmware images Related work items: #471343
…UVM regressions Add .sdata/.srodata sections to output '.data' to include renamed sections defining reent (impure) in newlib Remove spurious object instance declaration in mbox_status callback to resolve NOA Related work items: #473025, #473038
… source data comes from the keyvault - forcing crypto operations with kv reads to write to a non readable register in SHA and HMAC - forcing privkey into kv reg when seed comes from KV Related work items: #460864
- fix for arb bug - masking direct req dv when not granted - better fix for held transactions by not toggling priority until grant is consumed - adding assertion to catch direct request collision with soc req Related work items: #473215
- adding valid pauser and lock to fuse registers - added integration parameter for setting fuse valid pauser Related work items: #434165
…celerator max stall in str... updating max wait count to 20 to account for sha accelerator max stall in streaming mode Related work items: #473634
functional coverage for AHB bus logic Related work items: #475592
…de CPTRA_FUSE_PAUSER_VALID... Updated register headers and soc_ifc tests to include CPTRA_FUSE_PAUSER_VALID & CPTRA_FUSE_PAUSER_LOCK. Related work items: #476883
Add a constraint on AHB read/write mode to prevent data corruption during sequence that injects random Mailbox read/write activity. Resolves regression failure: https://dev.azure.com/ms-tsd/AHA_POC/_apps/hub/MSFTCPSDevOps.metadata-search-page.triage#/regressions/1585566/tests/401816121 Related work items: #477262
Update to prediction callback on mbox_execute so that end of mailbox flow properly clears the status field back to CMD_BUSY Resolves: https://dev.azure.com/ms-tsd/AHA_POC/_apps/hub/MSFTCPSDevOps.metadata-search-page.triage#/regressions/1585566/tests/401816564 Related work items: #477386
added ecc error Related work items: #475637, #475638, #475639
fixing veer rdc violations from uc rst to powergood Created a dedicated gated clock for uc that shuts off to cover both uc rst and warm rst. Related work items: #535520
Move UVM APB agent onto cptra_noncore_rst_b domain. Fix a script issue when compiling multiple fw images (for uvmf_caliptra_top) so that correct object dependencies are used to build each image. Reduce the very large delays that may be randomized for the rand_delay sequence, as this adds little value to the testcase and extends timeouts. Fix for FSM check flagging false failures in the soc_mbox_handler sequence for random invalid register access injection. Related work items: #536549
… key test - enhancing mbox sha to behave more like how ROM will do FIPS test, using direct access path to put the KAT into some region of the mailbox - adding a smoke test that zeroizes during kv operation and confirms that dest valid bits are not set - adding zeroize partial key test to L0 regression Related work items: #527027
fixing sha sequence for constraint solver and issue with start address overlapping the existing data Related work items: #539409
Add cycle-accurate prediction of Watchdog timer interrupt assertion (so it isn't interrupted by random reads to the global_intr reg) Use re-randomization instead of manual assignment for start_addr in sha_accel sequence to adhere to all constraints. Related work items: #539423
Dev msft 20230906
Merge dev-goog -> dev-integrate
- WDT sequence update to include NMI checking and reset assertion - Predictor updates to take care of WDT operation - Runtime fw updates for WDT behavior, randomize smaller timeout periods in cascade mode - Caleb's fix to handle fatal error during reset - Minor addition to clk gating test to latch debug mode Related work items: #468172
…htly regressions Addressed a few failures in directed nightly regressions * INTR_BLOCK_RF registers -- bit field correction and WO sticky register test checks. * FUSE_PAUSER test -- FUSE_ANTI_ROLLBACK register writes needed to be held off until ready_for_fuses. * PWRON_RESET test -- GENERIC_INPUT_WIRES needed to affect init value for power-on checks; not their latched versions. Related work items: #540928
…jection testcase, fix for UVM edge case Use modports at every port connection point for the EL2 Mem export interface, which resolves #179 Add a new UVM testcase that injects double bit errors into the Mailbox SRAM during a mailbox flow operation and checks the response Fix for an edge case in a UVM test where response data size (communicated through in-band data payload) is corrupted as part of an error injection test in the uvmf_soc_ifc suite. Related work items: #519675
Dev msft 20230913
Dev-msft -> dev-integrate Adds: Merged PR 122518: Enable NMI scenario in WDT test Merged PR 123605: TB related fixes to address soc_Ifc_tb directed nig… Merged PR 123991: EL2 Mem Interface modports, new double-bit error in… Merge pull request #214 from chipsalliance/dev-msft-20230913
#208) * Removing default case from unique case in csrnc_reg_top and entropy_src_reg_top * Add reg_rdata_next = '0 to prevent X prop
Fixing LEC Formality_Error_Code reported in caliptra_prim_assert_sec_…
Merge dev-integrate -> main
kgugala
approved these changes
Oct 3, 2023
Thanks for the review. Rebasing is generally problematic because it causes new commit hashes to be generated for the entire incoming history. We don't want new hashes because this branch will eventually be merged back towards main, and that would produce duplicate commits and merge headaches. |
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I meant fast forward merge here - if we do regular merge we'll add a merge commit not present on main. But if that is OK, we can do a regular merge |
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