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Reintegrate main -> dev-public #238

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3e0d8ee
Merge pull request #51 from chipsalliance/dev-integrate
bharatpillilli Apr 5, 2023
d1c7f89
Merge pull request #87 from chipsalliance/dev-public
anjpar May 10, 2023
bef573c
Fixed duplicate build_matrix in build-test-verilator.yml
anjpar May 15, 2023
d334c84
Merge pull request #88 from chipsalliance/dev-integrate
bharatpillilli May 15, 2023
02f97ac
Merge branch 'main' into dev-goog
howardtr May 20, 2023
b86ce18
Added 2:1 AHB lite mux on LSU and SB buses to allow debug access to p…
mkurc-ant May 29, 2023
d107d4f
Update VeeR codebase (#93)
mkurc-ant May 30, 2023
29b0c80
Updating verilator to 5.010 (#91)
howardtr Jun 1, 2023
4650034
Renaming prim/prim_generic -> caliptra_prim/caliptra_prim_generic (#103)
howardtr Jun 2, 2023
83af4eb
Fixes to get caliptra_top to elaborate in dev-goog with internal tool…
howardtr Jun 2, 2023
d718526
Merge pull request #106 from chipsalliance/main
anjpar Jun 6, 2023
88d2191
Fixed incorrect connection of u_sb_lsu_ahb_mux.hreadyout_i (#105)
mkurc-ant Jun 7, 2023
c3ef786
Merged PR 108066: soc_ifc_tb build fix and tweaks to address register…
May 11, 2023
d9071b1
Merged PR 108435: SHA512 Acc CSR predictor logic
Nitsirks May 15, 2023
cb24da7
resolved merge conflict
calebofearth May 15, 2023
c01085a
Merged PR 108405: UVMF SOC IFC Regression fixes - reg model race cond…
calebofearth May 15, 2023
c49696f
Merged PR 108284: Adding ROM and Firmware images
vmhatre May 16, 2023
97aec38
Merged PR 108852: Fix for LD (linker) error and Null-Object error in …
calebofearth May 17, 2023
6563a0a
Merged PR 108786: Results from cryptos always go into kv reg when the…
Nitsirks May 17, 2023
9fa141e
Merged PR 108955: Fix for soc ifc arb deadlock bug
Nitsirks May 18, 2023
fae98ab
Merged PR 108620: valid pauser protection for FUSE access
Nitsirks May 18, 2023
f25cb32
Merged PR 109155: updating max wait count to 20 to account for sha ac…
Nitsirks May 18, 2023
c593b38
Merged PR 109711: functional coverage for AHB bus logic
Nitsirks May 24, 2023
7879c18
resolved merge conflict
calebofearth May 25, 2023
c58689c
Merged PR 109957: Updated register headers and soc_ifc tests to inclu…
May 25, 2023
abb183f
Merged PR 110064: UVM Mailbox Interference Sequence fix
calebofearth May 25, 2023
73f37da
Merged PR 110097: UVM mailbox status reg prediction fix
calebofearth May 25, 2023
3aeeac2
resolved merge conflict
May 30, 2023
dd20e2b
resolved merge conflict
calebofearth Jun 1, 2023
6fb9bdf
Merged PR 110590: added ecc error
mojtaba-bisheh Jun 1, 2023
2782d89
Merged PR 110820: added intr to all smoke_test
mojtaba-bisheh Jun 3, 2023
d4037f8
resolved merge conflict
upadhyayulakiran Jun 5, 2023
434d4da
resolved merge conflict
Jun 5, 2023
377f7f2
Merged PR 110878: SOC_IFC UVM bench fixes to account for RAS feature
calebofearth Jun 5, 2023
e4814a5
Merged PR 110881: KV/PV coverage
upadhyayulakiran Jun 6, 2023
f131b8b
Merged PR 110447: scheduled coverage pipeline to run at noon everyday
Jun 6, 2023
0eced8d
resolved merge conflict
calebofearth Jun 7, 2023
2c69c22
Merged PR 111332: updated pipeline cron job to run at 8am instead of …
Jun 7, 2023
bebf2f3
Merged PR 110104: WDT+CG fixes and coverage
upadhyayulakiran Jun 7, 2023
6176624
Merged PR 111340: Fix for KV/PV build errors in regression
upadhyayulakiran Jun 7, 2023
36828e5
Merged PR 111326: SOC IFC functional coverage
Nitsirks Jun 8, 2023
67fe5cf
Merged PR 111486: fix for missing coverage file from uvmf compile.yml
Nitsirks Jun 8, 2023
ec33296
updated timestamp
Jun 8, 2023
0f27657
fixed duplicate declaration causing Verilator smoke test to fail
Jun 8, 2023
6e21a8b
Merge pull request #109 from chipsalliance/dev-msft-20230608
anjpar Jun 9, 2023
bdf8e39
Merge pull request #110 from chipsalliance/dev-msft
anjpar Jun 9, 2023
d895b27
Merge branch 'dev-integrate' into dev-goog
anjpar Jun 9, 2023
133ac2c
Merge pull request #111 from chipsalliance/dev-goog
anjpar Jun 9, 2023
3ffe3c7
Merge pull request #112 from chipsalliance/dev-integrate
anjpar Jun 9, 2023
5ef9a1e
Reverted addition of the scan_rst_l input to VeeR-EL2 core (#102)
mkurc-ant Jun 14, 2023
6756337
Merge pull request #119 from chipsalliance/dev-integrate
bharatpillilli Jun 20, 2023
9f051ff
Merge pull request #123 from chipsalliance/main
anjpar Jun 21, 2023
3c0538d
Merged PR 111808: UVM reg model prediction bug fix
calebofearth Jun 12, 2023
715c50f
Merged PR 111394: UVM promote smoke tests and ROM regression
calebofearth Jun 12, 2023
cf35735
Merged PR 111981: Added separate pipeline yaml files for regression r…
Jun 13, 2023
71aa2cb
Merged PR 112173: UVM fix for regression failure from SHA accel opera…
calebofearth Jun 14, 2023
eafe2eb
Merged PR 112398: Tweaks to Nightly ROM test
calebofearth Jun 15, 2023
42aaa36
Merged PR 112299: Tests for new soc_ifc registers that were causing i…
Jun 15, 2023
c535bf3
Merged PR 112549: LMS fuse addition and SHA512-ACC FIPS explicit lock…
Jun 16, 2023
a3fb0dd
Merged PR 112394: fw update reset sequence fixed and added to random …
Nitsirks Jun 17, 2023
b0933f9
Merged PR 112589: Add UVM coverage subscribers
calebofearth Jun 19, 2023
ecec81d
Merged PR 112907: Bugfixes from regressions
Nitsirks Jun 20, 2023
278562c
Merged PR 112692: FSM prediction improvements; interrupt timing fix
calebofearth Jun 20, 2023
191ca1a
Merged PR 113035: SHA512 Coverage
mojtaba-bisheh Jun 21, 2023
1288106
Merge branch 'main' into dev-goog-ci
howardtr Jun 21, 2023
9fdc32d
Updating to verilator 5.012
howardtr Jun 21, 2023
c016a31
Merge pull request #124 from chipsalliance/dev-msft-20230621
anjpar Jun 21, 2023
bba1ef5
Merge pull request #127 from chipsalliance/dev-goog-ci
howardtr Jun 21, 2023
965a7b4
Remove QSPI inout port and replace with input/output (#134)
howardtr Jun 24, 2023
90d0882
Enable using OpenOCD for interactive debugging of simulated Caliptra …
mkurc-ant Jun 26, 2023
dce3312
Merge pull request #142 from chipsalliance/dev-msft
calebofearth Jun 29, 2023
d6af416
Merge pull request #141 from chipsalliance/dev-goog
calebofearth Jun 29, 2023
61fb5bd
Merge pull request #143 from chipsalliance/dev-integrate
bharatpillilli Jun 29, 2023
540bb9c
Merge pull request #146 from chipsalliance/main
calebofearth Jun 29, 2023
7b5cff4
Exclude some CI tests for Verilator (#132)
mkurc-ant Jul 10, 2023
5f942ae
Merged PR 113035: SHA512 Coverage
mojtaba-bisheh Jun 21, 2023
0b798a3
Merged PR 113151: Fix for mbox sequence base
calebofearth Jun 21, 2023
7c12fbf
Merged PR 113052: New UVM mailbox test cases - inject random delays
calebofearth Jun 22, 2023
d32995b
Merged PR 113246: SOC_IFC - Fix for HW ERROR registers with bad rsvd …
calebofearth Jun 23, 2023
3d56ef7
Merged PR 113010: RAS test for non fatal errors, WDT checks
upadhyayulakiran Jun 23, 2023
8311ef4
Merged PR 113659: Promote pipeline runtime optimizations
calebofearth Jun 24, 2023
d87f440
Merged PR 113388: added hmac smoke_test and update sha params
mojtaba-bisheh Jun 24, 2023
61cb878
Merged PR 113911: UVM regression timeout increase
calebofearth Jun 27, 2023
c090115
Merged PR 113936: Promote Pipeline - TRNG L0 regression speedup
calebofearth Jun 28, 2023
f8b74c3
Merged PR 114111: added sha256 and hmac cov
mojtaba-bisheh Jun 29, 2023
e462988
Merged PR 114374: extended pcr_nonce from 32-bit to 256-bit
mojtaba-bisheh Jun 29, 2023
0d9b13d
Merged PR 114587: New soc_ifc register tests, special cases including…
Jul 1, 2023
ce475e3
Merged PR 114881: UVM mailbox sequence fix for invalid PAUSER access …
calebofearth Jul 6, 2023
807de2b
Merged PR 114429: Merge dev-msft into MSFT internal repo
calebofearth Jul 7, 2023
4f1b1cb
Merged PR 114014: [UVM] Mailbox testcases for invalid behavior
calebofearth Jul 7, 2023
2a3beb5
Merged PR 114956: Clock gating tests for mbox, DOE and KV, related bu…
upadhyayulakiran Jul 7, 2023
b436906
Merged PR 113668: RDC clock gating fix for warm reset and masking for…
Nitsirks Jul 8, 2023
b5e5bfc
resolved merge conflict
Jul 11, 2023
052af07
Update build-test-verilator.yml with additional tests to exclude from…
anjpar Jul 11, 2023
245c078
Update verilator version to 5.012
anjpar Jul 11, 2023
f71a9aa
Merge pull request #149 from chipsalliance/dev-msft-20230710
anjpar Jul 12, 2023
3391887
Pre-built iccm_lock hex file (#133)
calebofearth Jul 13, 2023
2039687
Merged PR 115354: Fix for underread randomizing to a huge dataout rea…
calebofearth Jul 11, 2023
2c80ea9
Merged PR 114969: Updated rolling coverage to 14 days (previously 7) …
Jul 12, 2023
c1fd567
Merged PR 115404: UVM regression fixes for spurious predicted transac…
calebofearth Jul 13, 2023
7b5b64b
Merged PR 115744: TB environment and test for fuse pauser based reads…
Jul 13, 2023
5e1923a
Merged PR 115228: removing PSEL from read data and error paths per ti…
Nitsirks Jul 13, 2023
ce10589
Merge pull request #153 from chipsalliance/dev-msft-20230713
anjpar Jul 13, 2023
1be849d
Merge pull request #151 from chipsalliance/dev-msft
anjpar Jul 13, 2023
e40aae8
Merge pull request #154 from chipsalliance/dev-integrate
bharatpillilli Jul 14, 2023
4e11761
Remove security_state multi-driver that was erroneously re-introduced…
calebofearth Jul 18, 2023
b921a16
Merged PR 115522: Added ECC coverage
mojtaba-bisheh Jul 13, 2023
7540a61
Merged PR 115977: assigned scan_mode in ecc uvmf
mojtaba-bisheh Jul 14, 2023
313d47b
Merged PR 116845: Increase ROM size to 48KiB
calebofearth Jul 21, 2023
ecb06dd
Merged PR 117067: Additional ICCM_LOCK test checking
calebofearth Jul 24, 2023
aa1ad6e
Merged PR 117045: AHB 32->64 bit modification in soc_ifc_tb environme…
Jul 25, 2023
737b798
Merged PR 117214: Datavault/FLOW_STATUS register updates, JTAG access…
upadhyayulakiran Jul 25, 2023
b0fceeb
Merged PR 117402: fixed modular addition bug found by FPV
mojtaba-bisheh Jul 25, 2023
65d9934
Merged PR 117393: FIPS SOC register updates
upadhyayulakiran Jul 25, 2023
2928566
Merged PR 117208: added doe cbc nist test vectors
mojtaba-bisheh Jul 25, 2023
c236863
Updated timestamp
Jul 26, 2023
081d5a4
Updated spec and testplan documents
Jul 26, 2023
4721da9
Updated README.md with note about regression test list to run, and fi…
Jul 28, 2023
2c1d0af
Merge pull request #168 from chipsalliance/dev-msft-20230726
anjpar Jul 28, 2023
8c57748
Fixed typo in README.md
anjpar Jul 29, 2023
eede62c
Merge pull request #170 from chipsalliance/dev-msft
anjpar Jul 31, 2023
d792ce2
Merge pull request #172 from chipsalliance/dev-integrate
bharatpillilli Aug 1, 2023
9aa732e
Merged PR 116787: Add Mailbox ECC Error injection to UVM tb
calebofearth Jul 27, 2023
3c8ae28
Merged PR 118346: added SVA and coverage for modular operations
mojtaba-bisheh Aug 2, 2023
896ef91
Merged PR 118379: More RDC clean up and fuse valid pauser fix
Nitsirks Aug 4, 2023
45149d1
Merged PR 118100: UVM protocol error testcases
calebofearth Aug 7, 2023
4fdf169
Merged PR 118807: 2:1 Mux bugfix and added current read pointer to mb…
Nitsirks Aug 8, 2023
64a9993
Merged PR 118985: fixed mont mult bug in last reduction found by FPV
mojtaba-bisheh Aug 8, 2023
1ce58e6
Merged PR 118720: WDT in top-level UVM
upadhyayulakiran Aug 9, 2023
3c5058b
Updated timestamps for Release_notes.md and README.md
Aug 14, 2023
65c23bf
Updated integration spec and testplan
Aug 14, 2023
8bb19ac
Formal sha512 (#144)
ludwigatlubis Aug 14, 2023
30da89b
Merged PR 119192: soc_ifc_tb fixes and debug unlock logic fix
Nitsirks Aug 14, 2023
2997c9d
Merged PR 119559: UVM fixes for RDC reset timing changes
calebofearth Aug 15, 2023
4f85139
Merged PR 120028: added pcr invalid command
mojtaba-bisheh Aug 15, 2023
071060b
Merged PR 120140: bringing noncore reset out after rdc clk dis delay …
Nitsirks Aug 19, 2023
b2c3439
Merged PR 119732: ROM regression timeout fix
calebofearth Aug 21, 2023
5cf193b
Merged PR 120849: UVM Regression fixes
calebofearth Aug 21, 2023
bfab1a5
Merged PR 120675: KV UVM updates for clear and debug mode changes
upadhyayulakiran Aug 23, 2023
581213e
Merged PR 120994: Fix for bug 532683 - SHA Accel direct access doesn'…
Nitsirks Aug 23, 2023
719ca1e
Updated README and Release_Notes timestamps
Aug 24, 2023
d5b0ed4
Merge pull request #185 from chipsalliance/dev-msft-20230813
anjpar Aug 24, 2023
d824380
Merge pull request #192 from chipsalliance/dev-msft
anjpar Aug 25, 2023
76d7c90
Merge pull request #193 from chipsalliance/dev-integrate
bharatpillilli Aug 25, 2023
953fc1e
Merged PR 121265: UVM environment regression fixes
calebofearth Aug 25, 2023
aa38b7a
Merged PR 121551: TB + coverage and test updates for new soc_ifc regi…
Aug 25, 2023
5c684ee
Updated README and Release_Notes timestamps
Aug 25, 2023
4c52351
Merge pull request #195 from chipsalliance/dev-msft-20230825
anjpar Aug 26, 2023
1fa92a2
Merged PR 121625: UVM regression fixes and synthesis assert disable
calebofearth Aug 26, 2023
f9ca7d3
Merged PR 122136: fixing veer rdc violations from uc rst to powergood
Nitsirks Aug 30, 2023
7e0673a
Merged PR 122520: UVM regression fixes
calebofearth Sep 1, 2023
f0e3eac
Merged PR 122634: Enhancing sha mbox mode sequence and adding partial…
Nitsirks Sep 1, 2023
05fc998
Merged PR 122941: Fix for SHA mailbox mode sequence bug
Nitsirks Sep 6, 2023
de62bac
Merged PR 122950: UVM regression fix for WDT interrupt mis-prediction
calebofearth Sep 6, 2023
e951083
Remove MSFT internal collateral that was previously sync'd erroneously
calebofearth Sep 6, 2023
14ab9ae
Remove MSFT internal scripts
calebofearth Sep 6, 2023
42e2e41
Updated file hierarchy, timestamps, scripts desc
calebofearth Sep 6, 2023
91657a8
Updated integ spec w/ corrected diagrams
calebofearth Sep 6, 2023
ee61ae5
Merge pull request #200 from chipsalliance/dev-msft-20230906
calebofearth Sep 6, 2023
693a7a0
Merge pull request #196 from chipsalliance/dev-msft
calebofearth Sep 7, 2023
a251696
Merge pull request #202 from chipsalliance/dev-goog
calebofearth Sep 7, 2023
7bfc833
Fixing LEC Formality_Error_Code reported in caliptra_prim_assert_sec_…
howardtr Sep 8, 2023
555f7cc
Updates to diagrams, boot/reset requirements, ToC's, generic wires de…
calebofearth Sep 9, 2023
13b1506
Updated Release Notes for 1p0 (#212)
calebofearth Sep 12, 2023
647d710
Merged PR 122518: Enable NMI scenario in WDT test
upadhyayulakiran Sep 9, 2023
9d5f727
Merged PR 123605: TB related fixes to address soc_Ifc_tb directed nig…
Sep 12, 2023
ca3b71b
Merged PR 123991: EL2 Mem Interface modports, new double-bit error in…
calebofearth Sep 13, 2023
8ec2ed9
Merge pull request #214 from chipsalliance/dev-msft-20230913
calebofearth Sep 13, 2023
1db4ff3
Merge pull request #215 from chipsalliance/dev-msft
calebofearth Sep 13, 2023
a88ceb6
Release notes: Add one more bug fix to list
calebofearth Sep 13, 2023
00d2f45
Removing default case from unique case in csrnc_reg_top and entropy_s…
howardtr Sep 13, 2023
a333142
Merge pull request #213 from chipsalliance/dev-goog
bharatpillilli Sep 13, 2023
440a21d
Merge pull request #203 from chipsalliance/dev-integrate
bharatpillilli Sep 13, 2023
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Merged PR 108435: SHA512 Acc CSR predictor logic
Predictor logic for SHA accelerator registers

Handles checking for valid user, acquiring lock and setting user field, and soc has lock field

Related work items: #471827
  • Loading branch information
Nitsirks authored and Anjana Parthasarathy committed Jun 8, 2023
commit d9071b15a37b5060ebf39170a50594054fac056f
31 changes: 29 additions & 2 deletions src/soc_ifc/rtl/sha512_acc_csr.sv
Original file line number Diff line number Diff line change
@@ -201,6 +201,10 @@ module sha512_acc_csr (
logic next;
logic load_next;
} VALID;
struct packed{
logic next;
logic load_next;
} SOC_HAS_LOCK;
} STATUS;
struct packed{
struct packed{
@@ -436,6 +440,9 @@ module sha512_acc_csr (
struct packed{
logic value;
} VALID;
struct packed{
logic value;
} SOC_HAS_LOCK;
} STATUS;
struct packed{
struct packed{
@@ -719,7 +726,7 @@ module sha512_acc_csr (
always_comb begin
automatic logic [0:0] next_c = field_storage.EXECUTE.EXECUTE.value;
automatic logic load_next_c = '0;
if(decoded_reg_strb.EXECUTE && decoded_req_is_wr) begin // SW write
if(decoded_reg_strb.EXECUTE && decoded_req_is_wr && hwif_in.valid_user) begin // SW write
next_c = (field_storage.EXECUTE.EXECUTE.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]);
load_next_c = '1;
end else if(hwif_in.EXECUTE.EXECUTE.hwclr) begin // HW Clear
@@ -756,6 +763,25 @@ module sha512_acc_csr (
end
end
assign hwif_out.STATUS.VALID.value = field_storage.STATUS.VALID.value;
// Field: sha512_acc_csr.STATUS.SOC_HAS_LOCK
always_comb begin
automatic logic [0:0] next_c = field_storage.STATUS.SOC_HAS_LOCK.value;
automatic logic load_next_c = '0;
if(1) begin // HW Write
next_c = hwif_in.STATUS.SOC_HAS_LOCK.next;
load_next_c = '1;
end
field_combo.STATUS.SOC_HAS_LOCK.next = next_c;
field_combo.STATUS.SOC_HAS_LOCK.load_next = load_next_c;
end
always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin
if(~hwif_in.cptra_rst_b) begin
field_storage.STATUS.SOC_HAS_LOCK.value <= 'h0;
end else if(field_combo.STATUS.SOC_HAS_LOCK.load_next) begin
field_storage.STATUS.SOC_HAS_LOCK.value <= field_combo.STATUS.SOC_HAS_LOCK.next;
end
end
assign hwif_out.STATUS.SOC_HAS_LOCK.value = field_storage.STATUS.SOC_HAS_LOCK.value;
for(genvar i0=0; i0<16; i0++) begin
// Field: sha512_acc_csr.DIGEST[].DIGEST
always_comb begin
@@ -1525,7 +1551,8 @@ module sha512_acc_csr (
assign readback_array[6][0:0] = (decoded_reg_strb.EXECUTE && !decoded_req_is_wr) ? field_storage.EXECUTE.EXECUTE.value : '0;
assign readback_array[6][31:1] = '0;
assign readback_array[7][0:0] = (decoded_reg_strb.STATUS && !decoded_req_is_wr) ? field_storage.STATUS.VALID.value : '0;
assign readback_array[7][31:1] = '0;
assign readback_array[7][1:1] = (decoded_reg_strb.STATUS && !decoded_req_is_wr) ? field_storage.STATUS.SOC_HAS_LOCK.value : '0;
assign readback_array[7][31:2] = '0;
for(genvar i0=0; i0<16; i0++) begin
assign readback_array[i0*1 + 8][31:0] = (decoded_reg_strb.DIGEST[i0] && !decoded_req_is_wr) ? field_storage.DIGEST[i0].DIGEST.value : '0;
end
10 changes: 10 additions & 0 deletions src/soc_ifc/rtl/sha512_acc_csr_pkg.sv
Original file line number Diff line number Diff line change
@@ -22,8 +22,13 @@ package sha512_acc_csr_pkg;
logic next;
} sha512_acc_csr__STATUS__VALID__in_t;

typedef struct packed{
logic next;
} sha512_acc_csr__STATUS__SOC_HAS_LOCK__in_t;

typedef struct packed{
sha512_acc_csr__STATUS__VALID__in_t VALID;
sha512_acc_csr__STATUS__SOC_HAS_LOCK__in_t SOC_HAS_LOCK;
} sha512_acc_csr__STATUS__in_t;

typedef struct packed{
@@ -151,8 +156,13 @@ package sha512_acc_csr_pkg;
logic value;
} sha512_acc_csr__STATUS__VALID__out_t;

typedef struct packed{
logic value;
} sha512_acc_csr__STATUS__SOC_HAS_LOCK__out_t;

typedef struct packed{
sha512_acc_csr__STATUS__VALID__out_t VALID;
sha512_acc_csr__STATUS__SOC_HAS_LOCK__out_t SOC_HAS_LOCK;
} sha512_acc_csr__STATUS__out_t;

typedef struct packed{
3 changes: 3 additions & 0 deletions src/soc_ifc/rtl/sha512_acc_csr_uvm.sv
Original file line number Diff line number Diff line change
@@ -108,6 +108,7 @@ package sha512_acc_csr_uvm;
// Reg - sha512_acc_csr::STATUS
class sha512_acc_csr__STATUS extends uvm_reg;
rand uvm_reg_field VALID;
rand uvm_reg_field SOC_HAS_LOCK;

function new(string name = "sha512_acc_csr__STATUS");
super.new(name, 32, UVM_NO_COVERAGE);
@@ -116,6 +117,8 @@ package sha512_acc_csr_uvm;
virtual function void build();
this.VALID = new("VALID");
this.VALID.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0);
this.SOC_HAS_LOCK = new("SOC_HAS_LOCK");
this.SOC_HAS_LOCK.configure(this, 1, 1, "RO", 1, 'h0, 1, 1, 0);
endfunction : build
endclass : sha512_acc_csr__STATUS

4 changes: 3 additions & 1 deletion src/soc_ifc/rtl/sha512_acc_external_csr.rdl
Original file line number Diff line number Diff line change
@@ -95,7 +95,7 @@ reg {
For the Mailbox SHA Function, indicates that the SHA can begin execution.
[br]Caliptra Access: RW
[br]SOC Access: RW";
field {sw=rw; hw=r; hwclr;} EXECUTE=0;
field {sw=rw; hw=r; hwclr; swwe=valid_user;} EXECUTE=0;
} EXECUTE;

reg {
@@ -108,6 +108,8 @@ reg {
default hw = rw;
default resetsignal = cptra_rst_b;
field {desc = "Valid bit, indicating that the digest is complete";} VALID = 1'b0;
field {name = "SoC Acquired the Lock";
desc = "Indicates that the current lock was acquired by the SoC";} SOC_HAS_LOCK=1'b0;

} STATUS;

3 changes: 2 additions & 1 deletion src/soc_ifc/rtl/sha512_acc_top.sv
Original file line number Diff line number Diff line change
@@ -189,7 +189,8 @@ always_comb core_digest_valid_q = core_digest_valid & ~(init_reg | next_reg);
always_comb hwif_in.valid_user = hwif_out.LOCK.LOCK.value & ((~soc_has_lock & ~req_data.soc_req) |
(soc_has_lock & req_data.soc_req & (req_data.user == hwif_out.USER.USER.value)));
always_comb hwif_in.soc_req = req_data.soc_req;

always_comb hwif_in.STATUS.SOC_HAS_LOCK.next = soc_has_lock;

always_comb mode = hwif_out.MODE.MODE.value;
//mode encoding bit 0 determines 512 or 384.
always_comb sha_mode = mode[0] ? MODE_SHA_512 : MODE_SHA_384;
Original file line number Diff line number Diff line change
@@ -0,0 +1,89 @@
//----------------------------------------------------------------------
// SPDX-License-Identifier: Apache-2.0
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//----------------------------------------------------------------------

class soc_ifc_reg_cbs_sha512_acc_csr_LOCK_LOCK extends uvm_reg_cbs;

`uvm_object_utils(soc_ifc_reg_cbs_sha512_acc_csr_LOCK_LOCK)

string AHB_map_name = "soc_ifc_AHB_map";
string APB_map_name = "soc_ifc_APB_map";

// Function: post_predict
//
// Called by the <uvm_reg_field::predict()> method
// after a successful UVM_PREDICT_READ or UVM_PREDICT_WRITE prediction.
//
// ~previous~ is the previous value in the mirror and
// ~value~ is the latest predicted value. Any change to ~value~ will
// modify the predicted mirror value.
//
virtual function void post_predict(input uvm_reg_field fld,
input uvm_reg_data_t previous,
inout uvm_reg_data_t value,
input uvm_predict_e kind,
input uvm_path_e path,
input uvm_reg_map map);
sha512_acc_csr_ext rm; /* sha512_acc_csr_rm */
uvm_reg_block blk = fld.get_parent().get_parent(); /* sha512_acc_csr_rm */
if (!$cast(rm,blk)) `uvm_fatal ("SOC_IFC_REG_CBS", "Failed to get valid class handle")
if (map.get_name() == this.AHB_map_name) begin
case (kind) inside
UVM_PREDICT_READ: begin
// Rising edge on RS
// Reading lock when it is already locked has no effect, so
// only calculate predictions on acquiring lock
if (value & ~previous) begin
rm.STATUS.SOC_HAS_LOCK.predict(uvm_reg_data_t'(0));
end
else begin
`uvm_info("SOC_IFC_REG_CBS", $sformatf("post_predict called with kind [%p] has no effect. value: 0x%x previous: 0x%x", kind, value, previous), UVM_FULL)
end
end
UVM_PREDICT_WRITE: begin

end
default: begin
`uvm_info("SOC_IFC_REG_CBS", $sformatf("post_predict called with kind [%p] has no effect", kind), UVM_FULL)
end
endcase
end
else if (map.get_name() == this.APB_map_name) begin
case (kind) inside
UVM_PREDICT_READ: begin
// Rising edge on RS
// Reading lock when it is already locked has no effect, so
// only calculate predictions on acquiring lock
if (value & ~previous) begin
rm.STATUS.SOC_HAS_LOCK.predict(uvm_reg_data_t'(1));
end
else begin
`uvm_info("SOC_IFC_REG_CBS", $sformatf("post_predict called with kind [%p] has no effect. value: 0x%x previous: 0x%x", kind, value, previous), UVM_FULL)
end
end
UVM_PREDICT_WRITE: begin

end
default: begin
`uvm_info("SOC_IFC_REG_CBS", $sformatf("post_predict called with kind [%p] has no effect", kind), UVM_FULL)
end
endcase
end
else begin
`uvm_error("SOC_IFC_REG_CBS", "post_predict called through unsupported reg map!")
end
endfunction

endclass
Original file line number Diff line number Diff line change
@@ -492,6 +492,7 @@ package soc_ifc_reg_model_top_pkg;
`include "soc_ifc_reg_cbs_soc_ifc_reg_CPTRA_TRNG_STATUS_DATA_REQ.svh"
`include "soc_ifc_reg_cbs_soc_ifc_reg_CPTRA_TRNG_STATUS_DATA_WR_DONE.svh"
`include "soc_ifc_reg_cbs_soc_ifc_reg_CPTRA_TRNG_VALID_PAUSER_PAUSER.svh"
`include "soc_ifc_reg_cbs_sha512_acc_csr_LOCK_LOCK.svh"

// pragma uvmf custom define_register_classes end
// pragma uvmf custom define_block_map_coverage_class begin
@@ -580,6 +581,8 @@ package soc_ifc_reg_model_top_pkg;
soc_ifc_reg_cbs_soc_ifc_reg_CPTRA_TRNG_STATUS_DATA_WR_DONE soc_ifc_reg_CPTRA_TRNG_STATUS_DATA_WR_DONE_cb;
soc_ifc_reg_cbs_soc_ifc_reg_CPTRA_TRNG_VALID_PAUSER_PAUSER soc_ifc_reg_CPTRA_TRNG_VALID_PAUSER_PAUSER_cb;

soc_ifc_reg_cbs_sha512_acc_csr_LOCK_LOCK sha512_acc_csr_LOCK_LOCK_cb;

uvm_reg_field error_en_flds[$];
uvm_reg_field notif_en_flds[$];
uvm_reg_field error_sts_flds[$];
@@ -664,6 +667,7 @@ package soc_ifc_reg_model_top_pkg;
soc_ifc_reg_CPTRA_TRNG_STATUS_DATA_WR_DONE_cb = soc_ifc_reg_cbs_soc_ifc_reg_CPTRA_TRNG_STATUS_DATA_WR_DONE::type_id::create("soc_ifc_reg_CPTRA_TRNG_STATUS_DATA_WR_DONE_cb");
soc_ifc_reg_CPTRA_TRNG_VALID_PAUSER_PAUSER_cb = soc_ifc_reg_cbs_soc_ifc_reg_CPTRA_TRNG_VALID_PAUSER_PAUSER::type_id::create("soc_ifc_reg_CPTRA_TRNG_VALID_PAUSER_PAUSER_cb");

sha512_acc_csr_LOCK_LOCK_cb = soc_ifc_reg_cbs_sha512_acc_csr_LOCK_LOCK::type_id::create("sha512_acc_Csr_lock_lock_cb");
// Callbacks compute side-effects to other registers in the reg-model
// in response to 'do_predict'.
// 'do_predict' is invoked by the reg_predictor after receiving a transaction
@@ -724,6 +728,9 @@ package soc_ifc_reg_model_top_pkg;
uvm_reg_field_cb::add(soc_ifc_reg_rm.CPTRA_TRNG_STATUS .DATA_WR_DONE, soc_ifc_reg_CPTRA_TRNG_STATUS_DATA_WR_DONE_cb );
uvm_reg_field_cb::add(soc_ifc_reg_rm.CPTRA_TRNG_VALID_PAUSER .PAUSER , soc_ifc_reg_CPTRA_TRNG_VALID_PAUSER_PAUSER_cb );

/* -- sha512_acc_csr -- */
uvm_reg_field_cb::add(sha512_acc_csr_rm.LOCK.LOCK, sha512_acc_csr_LOCK_LOCK_cb);

// pragma uvmf custom construct_configure_build_registers_within_block end
// pragma uvmf custom add_registers_to_block_map begin
/* Top register model default map */
Original file line number Diff line number Diff line change
@@ -181,6 +181,10 @@ task soc_ifc_env_sha_accel_sequence::sha_accel_acquire_lock(output op_sts_e op_s
reg_model.sha512_acc_csr_rm.LOCK.read(reg_sts, data, UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(apb_user_obj));
report_reg_sts(reg_sts, "LOCK");
end
//Read the lock again to test predictor
configuration.soc_ifc_ctrl_agent_config.wait_for_num_clocks(200); // FIXME add more randomization on delay
reg_model.sha512_acc_csr_rm.LOCK.read(reg_sts, data, UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(apb_user_obj));
report_reg_sts(reg_sts, "LOCK");
op_sts = CPTRA_SUCCESS;
endtask

@@ -197,6 +201,14 @@ task soc_ifc_env_sha_accel_sequence::sha_accel_set_cmd(input sha_accel_op_s op);

reg_model.sha512_acc_csr_rm.DLEN.write(reg_sts, data, UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(apb_user_obj));
report_reg_sts(reg_sts, "DLEN");

//read back some fields to test predictor
reg_model.sha512_acc_csr_rm.USER.read(reg_sts, data, UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(apb_user_obj));
report_reg_sts(reg_sts, "USER");
reg_model.sha512_acc_csr_rm.MODE.read(reg_sts, data, UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(apb_user_obj));
report_reg_sts(reg_sts, "MODE");
reg_model.sha512_acc_csr_rm.DLEN.read(reg_sts, data, UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(apb_user_obj));
report_reg_sts(reg_sts, "DLEN");
endtask

task soc_ifc_env_sha_accel_sequence::sha_accel_push_datain(reg [3199:0][31:0] sha_block_data);
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