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Build(deps): Bump third_party/yosys from 6f3376c to 66734f5 #6087

Build(deps): Bump third_party/yosys from 6f3376c to 66734f5

Build(deps): Bump third_party/yosys from 6f3376c to 66734f5 #6087

Triggered via pull request December 5, 2024 07:09
Status Failure
Total duration 1h 17m 50s
Artifacts 49

main.yml

on: pull_request
Matrix: build-binaries
Emit Workflow Info
0s
Emit Workflow Info
Style check
1m 48s
Style check
Verify README Correctness (Installation From Sources)
41m 24s
Verify README Correctness (Installation From Sources)
Matrix: Large Designs Tests / opentitan_parse_report
Matrix: Parsing Tests / parsing-tests
Large Designs Tests  /  Ibex (Vivado synthesis)
6m 10s
Large Designs Tests / Ibex (Vivado synthesis)
Large Designs Tests  /  Ibex (F4PGA synthesis)
11m 8s
Large Designs Tests / Ibex (F4PGA synthesis)
Large Designs Tests  /  Opentitan 9d82960888 (synthesis)
33m 35s
Large Designs Tests / Opentitan 9d82960888 (synthesis)
Large Designs Tests  /  Opentitan (synthesis)
51m 41s
Large Designs Tests / Opentitan (synthesis)
Large Designs Tests  /  VeeR-EH1 (synthesis)
5m 0s
Large Designs Tests / VeeR-EH1 (synthesis)
Large Designs Tests  /  Black Parrot (AMD (Xilinx) FPGA synthesis)
15m 57s
Large Designs Tests / Black Parrot (AMD (Xilinx) FPGA synthesis)
Large Designs Tests  /  Black Parrot (ASIC synthesis)
41m 15s
Large Designs Tests / Black Parrot (ASIC synthesis)
Large Designs Tests  /  Black Parrot (AMD (Xilinx) with PySynlig)
39m 37s
Large Designs Tests / Black Parrot (AMD (Xilinx) with PySynlig)
Diff generated BSG Micro Designs tests  /  Parse and diff BSG Micro Designs
6m 8s
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs
Matrix: Formal Verification Tests / tests-formal-verification
Parsing Tests  /  Generate AST diff
1m 55s
Parsing Tests / Generate AST diff
Parsing Tests  /  Summary Generation
1m 37s
Parsing Tests / Summary Generation
Release Package
0s
Release Package
Verify README Correctness (Download And Run Release)
0s
Verify README Correctness (Download And Run Release)
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Annotations

1 error and 4 warnings
Formal Verification Tests / yosys
Process completed with exit code 1.
Large Designs Tests / VeeR-EH1 (synthesis)
No files were found with the provided path: tests/build/chipsalliance.org_cores_VeeR_EH1_1.9/synth-vivado/chipsalliance.org_cores_VeeR_EH1_1.9.edif. No artifacts will be uploaded.
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs
Some generated tests differ from the reference or were not generated at all. Check the test statuses in the workflow summary or `bsg_micro_designs_summary.md` in the artifacts.
Large Designs Tests / Black Parrot (ASIC synthesis)
No files were found with the provided path: build third_party/OpenROAD-flow-scripts/logs third_party/OpenROAD-flow-scripts/reports third_party/OpenROAD-flow-scripts/results. No artifacts will be uploaded.
Large Designs Tests / Opentitan (synthesis)
No files were found with the provided path: tests/build/lowrisc_systems_custom_tiny_chip_custom_tiny_nexysvideo_0.1/synth-yosys/lowrisc_systems_custom_tiny_chip_custom_tiny_nexysvideo_0.1.edif. No artifacts will be uploaded.

Artifacts

Produced during runtime
Name Size
binaries-asan
292 MB
binaries-package
23.2 MB
binaries-plugin
41.7 MB
binaries-pysynlig
651 MB
binaries-release
42 MB
bp_e_bp_unicore_cfg.edif
3.92 MB
bsg-logs
5.57 MB
bsg-outputs
1.73 MB
formal-verification-logs-simple
18.6 MB
formal-verification-logs-sv2v
62.9 MB
formal-verification-logs-yosys
50.2 MB
lowrisc_ibex_top_artya7_surelog_0.1.bit
105 KB
lowrisc_systems_top_earlgrey_nexysvideo_0.1.bit
616 KB
opentitan-logs-full
4.58 MB
opentitan-logs-quick
827 KB
plots_binaries-asan
106 KB
plots_binaries-package
148 KB
plots_binaries-plugin
147 KB
plots_binaries-pysynlig
174 KB
plots_binaries-release
153 KB
plots_blackparrot_synth_asic
244 KB
plots_blackparrot_synth_xilinx
102 KB
plots_blackparrot_synth_xilinx_python
232 KB
plots_build_tools
79.8 KB
plots_formal_verification_simple
113 KB
plots_formal_verification_sv2v
113 KB
plots_formal_verification_yosys
95.7 KB
plots_ibex_synth
44.5 KB
plots_ibex_synth_f4pga
80 KB
plots_opentitan_9d82960888_synth
192 KB
plots_opentitan_parse_report_full
85.1 KB
plots_opentitan_parse_report_quick
38 KB
plots_opentitan_synth
276 KB
plots_tests_asan_read_systemverilog
224 KB
plots_tests_asan_read_uhdm
167 KB
plots_tests_plugin_read_systemverilog
35.7 KB
plots_tests_plugin_read_uhdm
33 KB
plots_tests_release_read_systemverilog
34.7 KB
plots_tests_release_read_uhdm
33.2 KB
plots_veer_synth
35.6 KB
python_bp_e_bp_unicore_cfg.edif
3.92 MB
results_parsing_tests_asan_read_systemverilog Expired
1.6 MB
results_parsing_tests_asan_read_uhdm Expired
1.81 MB
results_parsing_tests_plugin_read_systemverilog Expired
1.53 MB
results_parsing_tests_plugin_read_uhdm Expired
1.78 MB
results_parsing_tests_release_read_systemverilog Expired
1.48 MB
results_parsing_tests_release_read_uhdm Expired
1.73 MB
tools
39.2 MB
top_artya7.bit
122 KB