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Build(deps): Bump third_party/yosys from `6f3376c` to `66734f5` #6087

Job	Run time
Build tools	10m 59s
Build Synlig Release	22m 32s
Emit Workflow Info	0s
Style check	1m 48s
Verify README Correctness (Installation From Sources)	41m 24s
Build Plugin	20m 25s
Build Synlig (ASAN)	16m 22s
Build Package	21m 44s
Build PySynlig	25m 47s
Large Designs Tests / Black Parrot (AMD (Xilinx) FPGA synthesis)	15m 57s
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs	6m 8s
Formal Verification Tests / simple	17m 9s
Large Designs Tests / Black Parrot (ASIC synthesis)	41m 15s
Formal Verification Tests / sv2v	16m 53s
Formal Verification Tests / yosys	14m 29s
Large Designs Tests / Black Parrot (AMD (Xilinx) with PySynlig)	39m 37s
Large Designs Tests / Ibex (Vivado synthesis)	6m 10s
Large Designs Tests / Ibex (F4PGA synthesis)	11m 8s
Large Designs Tests / Opentitan 9d82960888 (synthesis)	33m 35s
Large Designs Tests / Opentitan parsing (full/top-down)	12m 47s
Large Designs Tests / Opentitan (synthesis)	51m 41s
Large Designs Tests / VeeR-EH1 (synthesis)	5m 0s
Large Designs Tests / Opentitan parsing (quick)	5m 26s
Parsing Tests / Test read_systemverilog release	4m 21s
Parsing Tests / Test read_uhdm release	4m 8s
Parsing Tests / Test read_systemverilog plugin	4m 25s
Parsing Tests / Test read_uhdm plugin	4m 5s
Parsing Tests / Test read_systemverilog asan	39m 0s
Parsing Tests / Test read_uhdm asan	25m 11s
Parsing Tests / Summary Generation	1m 37s
Parsing Tests / Generate AST diff	1m 55s
Release Package	0s
Verify README Correctness (Download And Run Release)	0s
	8h 42m 58s

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