I2C Boss-worker device

This repository contains various attempts to implement an I2C protocol with VHDL.

Only i2c.vhd and i2c_slave.vhd implementations work.

Components

Variable	Type	Description	Keyword
bus_clk	Int	I2c Bus Clock Speed Cycles	GENERIC
sys_clk	Int	System Clock Speed Cycles	GENERIC
CLK	Bit	Alternating 0 or 1 signal	PORT
RESET	Bit	Reset	PORT
P	Bit	Pull Up Resistor	PORT
SDA	Bit	Serial Data Line	PORT
SCL	Bit	Stretch Clock	PORT

Variable	Type	Description	Keyword
trigger	Bit	Bit that either store or output the memory	PORT
input	Bit	Input bit	PORT
output	Bit	Output Bit	PORT

Variable	Type	Description	Keyword
sys_clk	Int	Clock on the entire device	GENERIC
bus_clk	Int	I2c Bus Clock	GENERIC
slave_addr	7 Bit	Reference Address	GENERIC
CLK	Bit	Clock	PORT
RESET	Bit	Reset Bit	PORT
SCL	Bit	Stretch Clock	PORT
SDA	Bit	Input Output Bit	PORT
P	Byte	8 bit pull up resistor	PORT

Name		Name	Last commit message	Last commit date
Latest commit History 40 Commits
copy		copy
scripts		scripts
Bram1_tb.vhd		Bram1_tb.vhd
Bram_tb.vhd		Bram_tb.vhd
CO_Proc.vhdl		CO_Proc.vhdl
FSM.vhd		FSM.vhd
FSM_tb.vhd		FSM_tb.vhd
I2c_TB.vhd		I2c_TB.vhd
I2c_multi_TB.vhd		I2c_multi_TB.vhd
ITB.vhd		ITB.vhd
Loader.vhd		Loader.vhd
MatMul.vhd		MatMul.vhd
README.md		README.md
bram.vhd		bram.vhd
bram_mat1.vhd		bram_mat1.vhd
bram_mat2.vhd		bram_mat2.vhd
coProc.vhd		coProc.vhd
i2c.vhd		i2c.vhd
i2c_slave.vhd		i2c_slave.vhd
load_tv.vhd		load_tv.vhd
master.vhdl		master.vhdl
master_tb.vhdl		master_tb.vhdl
ram.vhd		ram.vhd
ram_mat.vhd		ram_mat.vhd
shift_reg.vhd		shift_reg.vhd
validate.vhd		validate.vhd
validate_tb.vhd		validate_tb.vhd