Denise Timing

Amiga resolutions and clock

The Amiga has three resolutions (two with OCS); low resolution (lores), high resolution (hires) and super high resolution (superhires). These are exactly set to the following pixel clocks:

 CLOCK      PITCH       MODE       DEPTH
--------    -----    ----------    -----
 7.16MHz    140ns    lores         6 bpp
14.32MHz     70ns    hires         4 bpp
28.63MHz     35ns    superhires    2 bpp

OCS gives us only two clock signals to work with, 7M and CCK and as such we are not able to generate (without a PLL) an internal clock any faster than 7MHz. This limitation is relaxed on ECS with the phase-shifted 7MHz signal CDAC that allows us to recreate a 14MHz signal. All the internal logic, except for the pixel clock, will use the one 7MHz clock.

PIN #      DESIGNATION     FUNCTION                DEFINITION
-----      -----------     ------------------      ----------
 34        CDAC            CDAC clock                  I (ECS)
 35        7M              7.16 MHz                    I
 36        CCK             Color clock                 I

These are aligned as shown:

____                 _______________
    |_______________|               |_______   CCK (3.58MHz Color Clock)
____         _______         _______              
    |_______|       |_______|       |_______    7M (7.16MHz System Clock)

We can use this to recreate the CCKQ signal by XORing the two input clocks. This clock is important as we need it to capture the mouse quadrature signal (hence its name). Mouse inputs are muxed on the CCK which means CCKQ is the "safe time" to sample the signal.

____________                 _______________
            |_______________|                 CCKQ (3.58MHz Color Clock Quadrature)

Neither CCK or CCKQ should be used as CLOCKS (e.g., posedge or negedge) and should be used only as strobes (if structures).

ECS Improvements

As mentioned, ECS adds the CDAC which is a 7MHz phase-shifted signal. We can XOR the CDAC and 7M signals to produce a 14MHz signal. Using the negedge we can meet the superhires pixel clock required on ECS. However, this is only done by the RAMDAC side of Denise on the other side of a bank of dual port RAM which should naturally create a buffer for CDC issues.

____         _______         _______              
    |_______|       |_______|       |_______    7M (7.16MHz)
 _______         _______         _______  
|       |_______|       |_______|       |___  CDAC (7M Quadrature)
     ___     ___     ___     ___     ___
|___|   |___|   |___|   |___|   |___|   |___   14M (14.32MHz)