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Merge pull request openhwgroup#864 from pascalgouedo/dev_dd_pgo_doc
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User Manual updates
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@davideschiavone
davideschiavone authored Sep 5, 2023
2 parents 8c5bcde + b02bc43 commit 4d281cf
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2 changes: 1 addition & 1 deletion docs/source/corev_hw_loop.rst
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Expand Up @@ -77,7 +77,7 @@ The HWLoop constraints are:

- No memory ordering instructions (fence, fence.i) allowed in the HWLoop body.

- No privileged instructions (mret, dret, ecall, wfi) allowed in the HWLoop body, except for ebreak.
- No privileged instructions (mret, dret, wfi) allowed in the HWLoop body, except for ebreak and ecall.

The rationale of NOT generating any hardware exception when violating any of those constraints is that it would add resources
(32-bit adders and substractors needed for the third and fourth rules) which are costly in area and power consumption.
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22 changes: 11 additions & 11 deletions docs/source/instruction_set_extensions.rst
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Expand Up @@ -672,19 +672,19 @@ Bit Manipulation Encoding
+--------+----------------------+---------------+---------+------------+--------+------------+------------------------------------+
| 31: 30 | 29 : 25 | 24 : 20 | 19 : 15 | 14 : 12 | 11 : 7 | 6 : 0 | |
+--------+----------------------+---------------+---------+------------+--------+------------+------------------------------------+
| **f2** | **ls3[4:0]** | **ls2[4:0]** | **rs1** | **funct3** | **rD** | **opcode** | **Mnemonic** |
| **f2** | **Is3[4:0]** | **Is2[4:0]** | **rs1** | **funct3** | **rD** | **opcode** | **Mnemonic** |
+========+======================+===============+=========+============+========+============+====================================+
| 00 | Luimm5[4:0] | Iuimm5[4:0] | src | 000 | dest | 101 1011 | **cv.extract rD, rs1, Is3, Is2** |
| 00 | Luimm5[4:0] | Luimm5[4:0] | src | 000 | dest | 101 1011 | **cv.extract rD, rs1, Is3, Is2** |
+--------+----------------------+---------------+---------+------------+--------+------------+------------------------------------+
| 01 | Luimm5[4:0] | Iuimm5[4:0] | src | 000 | dest | 101 1011 | **cv.extractu rD, rs1, Is3, Is2** |
| 01 | Luimm5[4:0] | Luimm5[4:0] | src | 000 | dest | 101 1011 | **cv.extractu rD, rs1, Is3, Is2** |
+--------+----------------------+---------------+---------+------------+--------+------------+------------------------------------+
| 10 | Luimm5[4:0] | Iuimm5[4:0] | src | 000 | dest | 101 1011 | **cv.insert rD, rs1, Is3, Is2** |
| 10 | Luimm5[4:0] | Luimm5[4:0] | src | 000 | dest | 101 1011 | **cv.insert rD, rs1, Is3, Is2** |
+--------+----------------------+---------------+---------+------------+--------+------------+------------------------------------+
| 00 | Luimm5[4:0] | Iuimm5[4:0] | src | 001 | dest | 101 1011 | **cv.bclr rD, rs1, Is3, Is2** |
| 00 | Luimm5[4:0] | Luimm5[4:0] | src | 001 | dest | 101 1011 | **cv.bclr rD, rs1, Is3, Is2** |
+--------+----------------------+---------------+---------+------------+--------+------------+------------------------------------+
| 01 | Luimm5[4:0] | Iuimm5[4:0] | src | 001 | dest | 101 1011 | **cv.bset rD, rs1, Is3, Is2** |
| 01 | Luimm5[4:0] | Luimm5[4:0] | src | 001 | dest | 101 1011 | **cv.bset rD, rs1, Is3, Is2** |
+--------+----------------------+---------------+---------+------------+--------+------------+------------------------------------+
| 11 | 000, Luimm2[1:0] | Iuimm5[4:0] | src | 001 | dest | 101 1011 | **cv.bitrev rD, rs1, Is3, Is2** |
| 11 | 000, Luimm2[1:0] | Luimm5[4:0] | src | 001 | dest | 101 1011 | **cv.bitrev rD, rs1, Is3, Is2** |
+--------+----------------------+---------------+---------+------------+--------+------------+------------------------------------+

.. table:: Register Bit Manipulation operations encoding
Expand Down Expand Up @@ -771,7 +771,7 @@ General ALU operations
| | |
| | else rD = rs1 |
| | |
| | Note: If ls2 is equal to 0, |
| | Note: If Is2 is equal to 0, |
| | |
| | -2^(Is2-1) is equivalent to -1 while (2^(Is2-1)-1) is equivalent to 0. |
+-------------------------------------------+------------------------------------------------------------------------+
Expand All @@ -781,7 +781,7 @@ General ALU operations
| | |
| | else rD = rs1 |
| | |
| | Note: If ls2 is equal to 0, (2^(Is2-1)-1) is equivalent to 0. |
| | Note: If Is2 is equal to 0, (2^(Is2-1)-1) is equivalent to 0. |
+-------------------------------------------+------------------------------------------------------------------------+
| **cv.clipr rD, rs1, rs2** | if rs1 <= -(rs2+1), rD = -(rs2+1), |
| | |
Expand Down Expand Up @@ -926,9 +926,9 @@ General ALU Encoding
+------------+---------------+---------+------------+--------+------------+-----------------------------+
| **funct7** | **Is2[4:0]** | **rs1** | **funct3** | **rD** | **opcode** | |
+============+===============+=========+============+========+============+=============================+
| 011 1000 | Iuimm5[4:0] | src1 | 011 | dest | 010 1011 | **cv.clip rD, rs1, Is2** |
| 011 1000 | Luimm5[4:0] | src1 | 011 | dest | 010 1011 | **cv.clip rD, rs1, Is2** |
+------------+---------------+---------+------------+--------+------------+-----------------------------+
| 011 1001 | Iuimm5[4:0] | src1 | 011 | dest | 010 1011 | **cv.clipu rD, rs1, Is2** |
| 011 1001 | Luimm5[4:0] | src1 | 011 | dest | 010 1011 | **cv.clipu rD, rs1, Is2** |
+------------+---------------+---------+------------+--------+------------+-----------------------------+
| 011 1010 | src2 | src1 | 011 | dest | 010 1011 | **cv.clipr rD, rs1, rs2** |
+------------+---------------+---------+------------+--------+------------+-----------------------------+
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