Enhance code reusability for the compiler backends #167
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jserv
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Nov 23, 2024
src/riscv-codegen.c
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| */ | ||
| rv_reg soft_div_rd = __t0, divisor_mask = __t1; | ||
| rv_reg helper_reg, divisor_mask = __t1; |
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Instead of naming it helper_reg, how about interm, which is the abbreviated form of "intermediate"? i.e., place an intermediate register for the division/modulo and load-store instructions.
vacantron
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Nov 23, 2024
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Because of pushing a redundant commit, I will squash the commits later. |
After observing ARM and RISC-V backends, the instruction sequences of load and global load operations are very similar, and both of them just use a different register for two instructions. A similar situation occurs for store and global store operations. Therefore, this commit improves the compiler backends to reuse the same code more efficiently.
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Thank @DrXiao for contributing! |
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After observing ARM and RISC-V backends, I noticed that the instruction sequences of load and global load operations are very similar:
/* ARM backend */ if (ph2_ir->src0 > 4095) { emit(__movw(__AL, __r8, ph2_ir->src0)); emit(__movt(__AL, __r8, ph2_ir->src0)); - emit(__add_r(__AL, __r8, __sp, __r8)); /* OP_load */ + emit(__add_r(__AL, __r8, __r12, __r8)); /* OP_global_load */ emit(__lw(__AL, rd, __r8, 0)); } else - emit(__lw(__AL, rd, __sp, ph2_ir->src0)); /* OP_load */ + emit(__lw(__AL, rd, __r12, ph2_ir->src0)); /* OP_global_load */A similar case occurs for store and global store operations.
Thus, this pull request improves code reusability for the compiler backends.