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LFSR #1

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Mar 10, 2024
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Merged

LFSR #1

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289c76b
Added LFSR
nblei Mar 10, 2024
269a23b
Changed namespace
nblei Mar 10, 2024
8352105
Set as pub
nblei Mar 10, 2024
67d6c40
Merge branch 'main' into lfsr
nblei Mar 10, 2024
da723ed
Added doc comments, and changed from if-else to case statement
nblei Mar 10, 2024
7558f8f
Merge branch 'lfsr' of github.com:nblei/veryl-std into lfsr
nblei Mar 10, 2024
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168 changes: 168 additions & 0 deletions src/lfsr/lfsr_galois.veryl
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module lfsr_galois #(
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parameter SIZE : u32 = 64 ,
localparam tapvec: type = logic<SIZE>,
parameter TAPVEC: tapvec = if SIZE == 2 {
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2'h3
} else if SIZE == 2 {
2'h3
} else if SIZE == 3 {
3'h5
} else if SIZE == 4 {
4'h9
} else if SIZE == 5 {
5'h12
} else if SIZE == 6 {
6'h21
} else if SIZE == 7 {
7'h41
} else if SIZE == 8 {
8'h8e
} else if SIZE == 9 {
9'h108
} else if SIZE == 10 {
10'h204
} else if SIZE == 11 {
11'h402
} else if SIZE == 12 {
12'h829
} else if SIZE == 13 {
13'h100d
} else if SIZE == 14 {
14'h2015
} else if SIZE == 15 {
15'h4001
} else if SIZE == 16 {
16'h8016
} else if SIZE == 17 {
17'h10004
} else if SIZE == 18 {
18'h20013
} else if SIZE == 19 {
19'h40013
} else if SIZE == 20 {
20'h80004
} else if SIZE == 21 {
21'h100002
} else if SIZE == 22 {
22'h200001
} else if SIZE == 23 {
23'h400010
} else if SIZE == 24 {
24'h80000d
} else if SIZE == 25 {
25'h1000004
} else if SIZE == 26 {
26'h2000023
} else if SIZE == 27 {
27'h4000013
} else if SIZE == 28 {
28'h8000004
} else if SIZE == 29 {
29'h10000002
} else if SIZE == 30 {
30'h20000029
} else if SIZE == 31 {
31'h40000004
} else if SIZE == 32 {
32'h80000057
} else if SIZE == 33 {
33'h100000029
} else if SIZE == 34 {
34'h200000073
} else if SIZE == 35 {
35'h400000002
} else if SIZE == 36 {
36'h80000003b
} else if SIZE == 37 {
37'h100000001f
} else if SIZE == 38 {
38'h2000000031
} else if SIZE == 39 {
39'h4000000008
} else if SIZE == 40 {
40'h800000001c
} else if SIZE == 41 {
41'h10000000004
} else if SIZE == 42 {
42'h2000000001f
} else if SIZE == 43 {
43'h4000000002c
} else if SIZE == 44 {
44'h80000000032
} else if SIZE == 45 {
45'h10000000000d
} else if SIZE == 46 {
46'h200000000097
} else if SIZE == 47 {
47'h400000000010
} else if SIZE == 48 {
48'h80000000005b
} else if SIZE == 49 {
49'h1000000000038
} else if SIZE == 50 {
50'h200000000000e
} else if SIZE == 51 {
51'h4000000000025
} else if SIZE == 52 {
52'h8000000000004
} else if SIZE == 53 {
53'h10000000000023
} else if SIZE == 54 {
54'h2000000000003e
} else if SIZE == 55 {
55'h40000000000023
} else if SIZE == 56 {
56'h8000000000004a
} else if SIZE == 57 {
57'h100000000000016
} else if SIZE == 58 {
58'h200000000000031
} else if SIZE == 59 {
59'h40000000000003d
} else if SIZE == 60 {
60'h800000000000001
} else if SIZE == 61 {
61'h1000000000000013
} else if SIZE == 62 {
62'h2000000000000034
} else if SIZE == 63 {
63'h4000000000000001
} else if SIZE == 64 {
64'h800000000000000d
} else {
'0
},
) (
i_clk : input logic ,
i_en : input logic ,
i_set : input logic ,
i_setval: input logic<SIZE>,
o_val : output logic<SIZE>,
) {

var val_next: logic<SIZE>;

assign val_next[SIZE - 1] = o_val[0];
for i in 0..(SIZE - 1) :g_taps {
localparam k: u32 = SIZE - 2 - i;
if TAPVEC[k] :g_tap {
assign val_next[k] = if i_set {
i_setval[k]
} else {
o_val[k + 1] ^ o_val[0]
};
} else :g_notap {
assign val_next[k] = if i_set {
i_setval[k]
} else {
o_val[k + 1]
};
}
}

always_ff (i_clk) {
if i_en {
o_val = val_next;
}
}
}
83 changes: 83 additions & 0 deletions testbench/lfsr_galois_bench.sv
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module testbench;
parameter MAXSIZE = 24;
parameter MINSIZE = 2;

logic [MAXSIZE-1:MINSIZE] done;
logic [MAXSIZE-1:MINSIZE] working;
logic i_clk;

for (genvar i = MINSIZE; i < MAXSIZE; ++i) begin
initial $display ("Spawning LFSR of Size %d", i);
lfsr_galois_bench #(.SIZE(i)) u_lfsr(.i_clk, .done(done[i]), .working(working[i]));
end
default clocking
@(posedge i_clk);
endclocking

initial forever begin
##4
if (&done) begin
if (|working) begin
$display("Finishing Simulations with \033[32m100%% Success\033[0m");
end else begin
$display("Finishing Simulations with \033[31mErrors\033[0m");
end
$finish;
end
end

initial begin
i_clk = 1'b0;
forever #5 i_clk = ~i_clk;
end
endmodule

module lfsr_galois_bench #(parameter SIZE=64) (input i_clk, output logic done, output logic working);
logic [SIZE:0] limit;


logic i_en, i_set;
logic [SIZE-1:0] i_setval;
logic [SIZE-1:0] o_val;

std_lfsr_galois #(.SIZE(SIZE)) dut (.*);


default clocking
@(posedge i_clk);
endclocking


initial begin
int outvecs [logic[SIZE-1:0]];
working = 1'b1;
$display("Begining LFSR of Size %d", SIZE);
done = 1'b0;
i_en = 1'b1;
i_set = 1'b1;
i_setval = 16'h0001;

##2;

i_set = 1'b0;
limit = '1;
limit[0] = 1'b0;
limit[SIZE] = 1'b0;

for (int i = 0; i < limit; i += 1) begin
##1;
assert(0 == outvecs.exists(o_val));
working &= !outvecs.exists(o_val);
outvecs[o_val] = 1'b1;
end

done = 1'b1;

if (working)
$display("Succesfully Ending LFSR of Size %0d", SIZE);
else
$display("Failure Detecing in LFSR of size %0d", SIZE);

end

endmodule