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Merge pull request openhwgroup#866 from openhwgroup/dev
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@davideschiavone
davideschiavone authored Sep 5, 2023
2 parents 12d0c48 + 4d281cf commit ed9fe0a
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388 changes: 206 additions & 182 deletions bhv/cv32e40p_rvfi.sv
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11 changes: 8 additions & 3 deletions bhv/cv32e40p_tb_wrapper.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -210,7 +210,7 @@ module cv32e40p_tb_wrapper
.apu_en_i (cv32e40p_top_i.apu_req),
.apu_singlecycle_i(cv32e40p_top_i.core_i.ex_stage_i.apu_singlecycle),
.apu_multicycle_i (cv32e40p_top_i.core_i.ex_stage_i.apu_multicycle),
.apu_rvalid_i (cv32e40p_top_i.apu_rvalid)
.apu_rvalid_i (cv32e40p_top_i.core_i.ex_stage_i.apu_valid)
);
`endif

Expand Down Expand Up @@ -298,7 +298,7 @@ module cv32e40p_tb_wrapper
.apu_multicycle_i (cv32e40p_top_i.core_i.ex_stage_i.apu_multicycle),
.wb_contention_lsu_i(cv32e40p_top_i.core_i.ex_stage_i.wb_contention_lsu),
.wb_contention_i (cv32e40p_top_i.core_i.ex_stage_i.wb_contention),

.regfile_we_lsu_i (cv32e40p_top_i.core_i.ex_stage_i.regfile_we_lsu),
// .rf_we_alu_i (cv32e40p_top_i.core_i.id_stage_i.regfile_alu_we_fw_i),
// .rf_addr_alu_i (cv32e40p_top_i.core_i.id_stage_i.regfile_alu_waddr_fw_i),
// .rf_wdata_alu_i (cv32e40p_top_i.core_i.id_stage_i.regfile_alu_wdata_fw_i),
Expand Down Expand Up @@ -339,11 +339,12 @@ module cv32e40p_tb_wrapper
.rf_we_wb_i(cv32e40p_top_i.core_i.id_stage_i.regfile_we_wb_i),
.rf_addr_wb_i(cv32e40p_top_i.core_i.id_stage_i.regfile_waddr_wb_i),
.rf_wdata_wb_i(cv32e40p_top_i.core_i.id_stage_i.regfile_wdata_wb_i),
.regfile_alu_we_ex_i(cv32e40p_top_i.core_i.id_stage_i.regfile_alu_we_ex_o),

// APU
.apu_req_i (cv32e40p_top_i.core_i.apu_req_o),
.apu_gnt_i (cv32e40p_top_i.core_i.apu_gnt_i),
.apu_rvalid_i(cv32e40p_top_i.core_i.apu_rvalid_i),
.apu_rvalid_i(cv32e40p_top_i.core_i.ex_stage_i.apu_valid),

// Controller FSM probes
.ctrl_fsm_cs_i(cv32e40p_top_i.core_i.id_stage_i.controller_i.ctrl_fsm_cs),
Expand All @@ -367,6 +368,10 @@ module cv32e40p_tb_wrapper
.csr_tdata1_q_i (cv32e40p_top_i.core_i.cs_registers_i.tmatch_control_rdata),//gen_trigger_regs.tmatch_control_exec_q ),
.csr_tdata1_we_i(cv32e40p_top_i.core_i.cs_registers_i.gen_trigger_regs.tmatch_control_we),

.csr_tdata2_n_i (cv32e40p_top_i.core_i.cs_registers_i.tmatch_value_rdata),//csr_wdata_int ),
.csr_tdata2_q_i (cv32e40p_top_i.core_i.cs_registers_i.tmatch_value_rdata),//gen_trigger_regs.tmatch_control_exec_q ),
.csr_tdata2_we_i(cv32e40p_top_i.core_i.cs_registers_i.gen_trigger_regs.tmatch_value_we),

.csr_tinfo_n_i({16'h0, cv32e40p_top_i.core_i.cs_registers_i.tinfo_types}),
.csr_tinfo_q_i({16'h0, cv32e40p_top_i.core_i.cs_registers_i.tinfo_types}),

Expand Down
40 changes: 40 additions & 0 deletions bhv/insn_trace.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -15,6 +15,10 @@
this.m_csr.``CSR_NAME``_wdata = m_source.m_csr.``CSR_NAME``_wdata; \
this.m_csr.``CSR_NAME``_wmask = m_source.m_csr.``CSR_NAME``_wmask;

`define INIT_CSR(CSR_NAME) \
this.m_csr.``CSR_NAME``_we = '0; \
this.m_csr.``CSR_NAME``_wmask = '0;

class insn_trace_t;
bit m_valid;
logic [63:0] m_order;
Expand All @@ -38,6 +42,7 @@

logic m_fflags_we_non_apu;
logic m_frm_we_non_apu;
logic m_fcsr_we_non_apu;
logic [5:0] m_rs1_addr;
logic [5:0] m_rs2_addr;
logic [31:0] m_rs1_rdata;
Expand Down Expand Up @@ -148,9 +153,40 @@
this.m_trap = 1'b0;
this.m_fflags_we_non_apu = 1'b0;
this.m_frm_we_non_apu = 1'b0;
this.m_fcsr_we_non_apu = 1'b0;
this.m_instret_cnt = 0;
endfunction

function void init_csr();
`INIT_CSR(mstatus)
`INIT_CSR(misa)
`INIT_CSR(mie)
`INIT_CSR(mtvec)
`INIT_CSR(mcountinhibit)
`INIT_CSR(mscratch)
`INIT_CSR(mepc)
`INIT_CSR(mcause)
`INIT_CSR(minstret)
`INIT_CSR(mip)
`INIT_CSR(tdata1)
`INIT_CSR(tdata2)
`INIT_CSR(tinfo)
`INIT_CSR(dcsr)
`INIT_CSR(dpc)
`INIT_CSR(dscratch0)
`INIT_CSR(dscratch1)
`INIT_CSR(mvendorid)
`INIT_CSR(marchid)
`INIT_CSR(fflags)
`INIT_CSR(frm )
`INIT_CSR(fcsr )
`INIT_CSR(lpstart0 )
`INIT_CSR(lpend0 )
`INIT_CSR(lpcount0 )
`INIT_CSR(lpstart1 )
`INIT_CSR(lpend1 )
`INIT_CSR(lpcount1 )
endfunction
/*
*
*/
Expand Down Expand Up @@ -189,6 +225,7 @@
this.m_trap = 1'b0;
this.m_fflags_we_non_apu = 1'b0;
this.m_frm_we_non_apu = 1'b0;
this.m_fcsr_we_non_apu = 1'b0;
this.m_csr.mcause_we = '0;
if (is_compressed_id_i) begin
this.m_insn[31:16] = '0;
Expand All @@ -213,6 +250,8 @@
this.m_mem.wmask = '0;
this.m_mem.rdata = '0;
this.m_mem.wdata = '0;

init_csr();
endfunction

function logic [63:0] get_order_for_trap();
Expand Down Expand Up @@ -256,6 +295,7 @@
this.m_trap = m_source.m_trap;
this.m_fflags_we_non_apu = m_source.m_fflags_we_non_apu;
this.m_frm_we_non_apu = m_source.m_frm_we_non_apu ;
this.m_fcsr_we_non_apu = m_source.m_fcsr_we_non_apu;

this.m_mem = m_source.m_mem;
//CRS
Expand Down
15 changes: 15 additions & 0 deletions bhv/pipe_freeze_trace.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -94,6 +94,7 @@ typedef struct {
logic apu_multicycle;
logic wb_contention_lsu;
logic wb_contention;
logic regfile_we_lsu;

logic branch_in_ex;
logic branch_decision_ex;
Expand Down Expand Up @@ -121,6 +122,7 @@ typedef struct {
logic rf_we_wb;
logic [5:0] rf_addr_wb;
logic [31:0] rf_wdata_wb;
logic rf_alu_we_ex;
// LSU
logic [31:0] lsu_rdata_wb;

Expand Down Expand Up @@ -436,6 +438,7 @@ task monitor_pipeline();
r_pipe_freeze_trace.apu_multicycle = apu_multicycle_i;
r_pipe_freeze_trace.wb_contention_lsu = wb_contention_lsu_i;
r_pipe_freeze_trace.wb_contention = wb_contention_i;
r_pipe_freeze_trace.regfile_we_lsu = regfile_we_lsu_i;

r_pipe_freeze_trace.branch_in_ex = branch_in_ex_i;
r_pipe_freeze_trace.branch_decision_ex = branch_decision_ex_i;
Expand Down Expand Up @@ -463,6 +466,7 @@ task monitor_pipeline();
r_pipe_freeze_trace.rf_we_wb = rf_we_wb_i;
r_pipe_freeze_trace.rf_addr_wb = rf_addr_wb_i;
r_pipe_freeze_trace.rf_wdata_wb = rf_wdata_wb_i;
r_pipe_freeze_trace.rf_alu_we_ex = regfile_alu_we_ex_i;
// LSU
r_pipe_freeze_trace.lsu_rdata_wb = lsu_rdata_wb_i;

Expand Down Expand Up @@ -676,6 +680,17 @@ task monitor_pipeline();
r_pipe_freeze_trace.hwloop.counter_n = hwlp_counter_n_i;

compute_csr_we();

//If fcsr_we has triggered, then fflags_we and frm_we should also be triggered
if (r_pipe_freeze_trace.csr.fcsr_we) begin
r_pipe_freeze_trace.csr.fflags_we = 1'b1;
r_pipe_freeze_trace.csr.frm_we = 1'b1;
end else begin
if (r_pipe_freeze_trace.csr.fflags_we || r_pipe_freeze_trace.csr.frm_we) begin
r_pipe_freeze_trace.csr.fcsr_we = 1'b1;
end
end

if (csr_fcsr_fflags_we_i) begin
r_pipe_freeze_trace.csr.fflags_we = 1'b1;
r_pipe_freeze_trace.csr.fcsr_we = 1'b1;
Expand Down
15 changes: 9 additions & 6 deletions docs/source/corev_hw_loop.rst
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Expand Up @@ -46,7 +46,8 @@ Following constraints must be respected by any toolchain compiler or by hand-wri

In order to catch **as early as possible** those software exceptions when executing a program either
on a verification Reference Model or on a virtual platform Instruction Set Simulator, ``those model/simulation platforms
must generate a fatal error`` with a meaningfull message related to Hardware Loops constraints violation.
should generate an error`` with a meaningfull message related to Hardware Loops constraints violation.
Those constraint checks could be done only for each instruction in the hardware loop body, meaning when (lpstartX <= PC <= lpendX - 4) and (lpcountX > 0).

The HWLoop constraints are:

Expand All @@ -63,6 +64,8 @@ The HWLoop constraints are:
- When both loops are nested, the End address of the outermost HWLoop (must be #1) must be at least 2
instructions further than the End address of the innermost HWLoop (must be #0),
i.e. HWLoop[1].endaddress >= HWLoop[0].endaddress + 8.
Remark: To avoid to add 2 NOPs in case nothing can be put there by the compiler, lpcount setting of the the inner loop could be moved after it
without forgetting to add the same in the preamble before the outer loop start address.

- HWLoop must always be entered from its start location (no branch/jump to a location inside a HWLoop body).

Expand All @@ -74,7 +77,7 @@ The HWLoop constraints are:

- No memory ordering instructions (fence, fence.i) allowed in the HWLoop body.

- No privileged instructions (mret, dret, ecall, wfi) allowed in the HWLoop body, except for ebreak.
- No privileged instructions (mret, dret, wfi) allowed in the HWLoop body, except for ebreak and ecall.

The rationale of NOT generating any hardware exception when violating any of those constraints is that it would add resources
(32-bit adders and substractors needed for the third and fourth rules) which are costly in area and power consumption.
Expand Down Expand Up @@ -111,17 +114,17 @@ Below an assembly code example of a nested HWLoop that computes a matrix additio
".balign 4;"
"cv.endi 0, endZ;"
"cv.starti 0, startZ;"
"cv.count 0, %[N];"
"any instructions here"
".balign 4;"
".option norvc;"
"startO:;"
" cv.count 0, %[N];"
" startZ:;"
" addi %[i], %[i], 1;"
" addi %[i], %[i], 1;"
" addi %[i], %[i], 1;"
" endZ:;"
" addi %[j], %[j], 2;"
" cv.count 0, %[N];"
" addi %[j], %[j], 2;"
"endO:;"
: [i] "+r" (i), [j] "+r" (j)
Expand All @@ -132,6 +135,6 @@ Below an assembly code example of a nested HWLoop that computes a matrix additio
At the beginning of the HWLoop, the registers %[i] and %[j] are 0.
The innermost loop, from startZ to (endZ - 4), adds to %[i] three times 1 and
it is executed 10x10 times. Whereas the outermost loop, from startO to (endO - 4),
executes 10 times the innermost loop and adds two times 2 to the register %[j].
At the end of the loop, the register %[i] contains 300 and the register %[j] contains 40.
executes 10 times the innermost loop and adds 2 to the register %[j].
At the end of the loop, the register %[i] contains 300 and the register %[j] contains 20.

22 changes: 11 additions & 11 deletions docs/source/instruction_set_extensions.rst
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Original file line number Diff line number Diff line change
Expand Up @@ -672,19 +672,19 @@ Bit Manipulation Encoding
+--------+----------------------+---------------+---------+------------+--------+------------+------------------------------------+
| 31: 30 | 29 : 25 | 24 : 20 | 19 : 15 | 14 : 12 | 11 : 7 | 6 : 0 | |
+--------+----------------------+---------------+---------+------------+--------+------------+------------------------------------+
| **f2** | **ls3[4:0]** | **ls2[4:0]** | **rs1** | **funct3** | **rD** | **opcode** | **Mnemonic** |
| **f2** | **Is3[4:0]** | **Is2[4:0]** | **rs1** | **funct3** | **rD** | **opcode** | **Mnemonic** |
+========+======================+===============+=========+============+========+============+====================================+
| 00 | Luimm5[4:0] | Iuimm5[4:0] | src | 000 | dest | 101 1011 | **cv.extract rD, rs1, Is3, Is2** |
| 00 | Luimm5[4:0] | Luimm5[4:0] | src | 000 | dest | 101 1011 | **cv.extract rD, rs1, Is3, Is2** |
+--------+----------------------+---------------+---------+------------+--------+------------+------------------------------------+
| 01 | Luimm5[4:0] | Iuimm5[4:0] | src | 000 | dest | 101 1011 | **cv.extractu rD, rs1, Is3, Is2** |
| 01 | Luimm5[4:0] | Luimm5[4:0] | src | 000 | dest | 101 1011 | **cv.extractu rD, rs1, Is3, Is2** |
+--------+----------------------+---------------+---------+------------+--------+------------+------------------------------------+
| 10 | Luimm5[4:0] | Iuimm5[4:0] | src | 000 | dest | 101 1011 | **cv.insert rD, rs1, Is3, Is2** |
| 10 | Luimm5[4:0] | Luimm5[4:0] | src | 000 | dest | 101 1011 | **cv.insert rD, rs1, Is3, Is2** |
+--------+----------------------+---------------+---------+------------+--------+------------+------------------------------------+
| 00 | Luimm5[4:0] | Iuimm5[4:0] | src | 001 | dest | 101 1011 | **cv.bclr rD, rs1, Is3, Is2** |
| 00 | Luimm5[4:0] | Luimm5[4:0] | src | 001 | dest | 101 1011 | **cv.bclr rD, rs1, Is3, Is2** |
+--------+----------------------+---------------+---------+------------+--------+------------+------------------------------------+
| 01 | Luimm5[4:0] | Iuimm5[4:0] | src | 001 | dest | 101 1011 | **cv.bset rD, rs1, Is3, Is2** |
| 01 | Luimm5[4:0] | Luimm5[4:0] | src | 001 | dest | 101 1011 | **cv.bset rD, rs1, Is3, Is2** |
+--------+----------------------+---------------+---------+------------+--------+------------+------------------------------------+
| 11 | 000, Luimm2[1:0] | Iuimm5[4:0] | src | 001 | dest | 101 1011 | **cv.bitrev rD, rs1, Is3, Is2** |
| 11 | 000, Luimm2[1:0] | Luimm5[4:0] | src | 001 | dest | 101 1011 | **cv.bitrev rD, rs1, Is3, Is2** |
+--------+----------------------+---------------+---------+------------+--------+------------+------------------------------------+

.. table:: Register Bit Manipulation operations encoding
Expand Down Expand Up @@ -771,7 +771,7 @@ General ALU operations
| | |
| | else rD = rs1 |
| | |
| | Note: If ls2 is equal to 0, |
| | Note: If Is2 is equal to 0, |
| | |
| | -2^(Is2-1) is equivalent to -1 while (2^(Is2-1)-1) is equivalent to 0. |
+-------------------------------------------+------------------------------------------------------------------------+
Expand All @@ -781,7 +781,7 @@ General ALU operations
| | |
| | else rD = rs1 |
| | |
| | Note: If ls2 is equal to 0, (2^(Is2-1)-1) is equivalent to 0. |
| | Note: If Is2 is equal to 0, (2^(Is2-1)-1) is equivalent to 0. |
+-------------------------------------------+------------------------------------------------------------------------+
| **cv.clipr rD, rs1, rs2** | if rs1 <= -(rs2+1), rD = -(rs2+1), |
| | |
Expand Down Expand Up @@ -926,9 +926,9 @@ General ALU Encoding
+------------+---------------+---------+------------+--------+------------+-----------------------------+
| **funct7** | **Is2[4:0]** | **rs1** | **funct3** | **rD** | **opcode** | |
+============+===============+=========+============+========+============+=============================+
| 011 1000 | Iuimm5[4:0] | src1 | 011 | dest | 010 1011 | **cv.clip rD, rs1, Is2** |
| 011 1000 | Luimm5[4:0] | src1 | 011 | dest | 010 1011 | **cv.clip rD, rs1, Is2** |
+------------+---------------+---------+------------+--------+------------+-----------------------------+
| 011 1001 | Iuimm5[4:0] | src1 | 011 | dest | 010 1011 | **cv.clipu rD, rs1, Is2** |
| 011 1001 | Luimm5[4:0] | src1 | 011 | dest | 010 1011 | **cv.clipu rD, rs1, Is2** |
+------------+---------------+---------+------------+--------+------------+-----------------------------+
| 011 1010 | src2 | src1 | 011 | dest | 010 1011 | **cv.clipr rD, rs1, rs2** |
+------------+---------------+---------+------------+--------+------------+-----------------------------+
Expand Down
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