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Firmware m2000
Target
Purpose
Versions
Structure
Boot process
OS and Libraries
Flashing
Interfaces
The firmware programs NAND array which loads bitstream into Altera Cyclone FPGA. Location of this chip:
- in P3X and P3S, it is on RC Main board.
The firmware is a synthesis of Lightbridge transmission technology and contains digital part of transmission system.
There are multiple versions, always unencrypted.
| Marking | Packages | Timestamp | Overview |
|---|---|---|---|
| 01.00.2107 | C1_FW_V01.03.0020 C1_FW_V01.03.00.21 C1_FW_V01.04.0030 C1_FW_V01.05.0070 C1_FW_V01.05.0080 C1_FW_V01.06.0000 C1_FW_v01.05.0071 C1_FW_v01.06.0001 C1_FW_v01.07.0000 C1_FW_v01.07.0002 C1_FW_v01.07.0030 C1_FW_v01.07.0040 C1_FW_v01.07.0060 C1_FW_v01.08.0000 C1_FW_v01.09.0000 P3S_FW_V01.01.0008 P3S_FW_V01.01.0009 P3S_FW_V01.02.0007 P3S_FW_V01.02.0008 P3S_FW_V01.03.0020 P3XS_FW_RC_V01.03.0020 P3X_FW_V01.01.0006 P3X_FW_V01.01.0008 P3X_FW_V01.01.0009 P3X_FW_V01.01.1003 P3X_FW_V01.01.1007 P3X_FW_V01.02.0006 P3X_FW_V01.03.0020 | 2015-04-30 ... 2016-11-10 | |
| 01.00.2321 | C1_FW_V01.00.0004 | 2015-09-22 | |
| 01.00.2322 | C1_FW_V01.00.0010 | 2015-11-19 |
The module contains the FPGA bitstream in a format proprietary to Altera FPGAs.
No analysis of the booting procedure were performed.
The module uses IP core integrated with Altera Quartus synthesis process.
TODO
TODO
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